Design, modeling, and fabrication of subhalf-micrometer CMOS transistors

We have designed, modeled, and fabricated subhalf-micrometer CMOS transistors. Two-dimensional process and device modeling was exercised extensively to determine the critical process parameters for device optimization. Buried-channel behavior of the p-channel FET's has been analyzed. The effect of lightly doped drain (LDD) structure on punch through voltage was studied. p and n-channel FET's with physical gate length as short as 0.3 µm, were fabricated using e-beam lithography, LDD structure, and silicided source-drains. The experimental devices show high transconductance and long-channel characteristics.