| 高速浮点FFT处理器的FPGA实现 |
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| 引用本文： | 丁智泉,张红雨.高速浮点FFT处理器的FPGA实现[J].四川理工学院学报(自然科学版),2006,19(1):60-63. |
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| 作者姓名： | 丁智泉 张红雨 |
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| 作者单位： | 电子科技大学电子工程学院,成都,610054 |
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| 摘 要： | 介绍了一种基于FPGA的1024点自定义24位浮点FFT处理器的设计。采用改进的蝶形运算单元,减小了系统的硬件消耗,改善了系统的性能。采用流水的方式提高了系统的处理速度,使计算与存储器读/写等操作协调一致;浮点算法使得系统具有较高的处理精度。该设计方法可以广泛应用于高速数字信号处理领域。
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| 关 键 词： | 可编程门阵列 浮点快速傅立叶处理器 蝶形 位反序 |
| 文章编号： | 1673-1549(2006)01-0060-04 |
| 修稿时间： | 2005年9月19日 |
Implementation of High-speed Floating - point FFT Processor on FPGA |
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| DING Zhi-quan,ZHANG Hong-yu.Implementation of High-speed Floating - point FFT Processor on FPGA[J].Journal of Sichuan University of Science & Engineering:Natural Science Editton,2006,19(1):60-63. |
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| Authors: | DING Zhi-quan ZHANG Hong-yu |
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| Abstract: | An FPGA-based design of a 24 bit floating-point FFT processor used to compute 1024 points FFT is presented.Because of the utilization of improved butterfly processor,hard-ware consumption is reduced and the performance is improved.As a result of adopting pipelined architecture,the processing speed is improved and the operations including calculation and reading/writing of storage harmoniously.High precision is achieved due to the inherence of the floating-point algorithm.The design method can widely be used in high speed digital signal processing fields. |
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| Keywords: | FPGA floating-point FFT processor butterfly bit-reversed |
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