基于FPGA的GIFT分组密码算法实现

GIFT算法作为PRESENT算法的改进版本，结构上更加简洁高效，在FPGA上运行时，性能仍然存在提升空间。对此提出了一种新的实现方案，通过将算法的40轮迭代计算优化为20轮迭，并将加解密与轮密钥生成操作并行执行。在xc6slx16 FPGA平台综合后，频率可达194 MHz,吞吐量可达1.2 Gbps,消耗时钟周期21个，结果表明，所提方法相比现有工作具有更好的性能表现和更少的时钟周期消耗，实现在FPGA上高速运行是切实可行的。

Implementation of GIFT block cipher algorithm based on FPGA

GIFT algorithm as an improved version of PRESENT algorithm, the structure is more concise and efficient, when it running on FPGA, the performance still has room for improvement. This paper proposed a new implementation scheme, by implemented the algorithm from a 40-round iterative computation to a 20-round iteration, and executed the encryption/decryption in parallel with the round key generation operations. After the proposed scheme used in xc6slx16 FPGA platform, frequency up to 194 MHz, throughput up to 1.2 Gbps, and it consumes 21 clock cycles. The results show that the proposed method has better performance and less clock cycle consumption compared to the existing work. It is practical to perform at high speed on FPGA.