二维非递归的低成本FIR滤波器设计方法

为降低有限冲激响应(Finite impulse response, FIR)数字滤波器的成本,提升可综合性,提出了一种基于系数矩阵的二维非递归优化算法,并进行了仿真.首先,对现有的数字滤波器优化算法进行了调研,比较了各优化算法的优势和不足;然后,对现有的一维非递归算法进行优化,提取一维非递归算法优化后的冗余项,得到了二维非递归优化算法,并分析了算法的复杂度;最后,生成多组滤波器分别对本算法与一维非递归算法,以及本算法和现有递归算法进行仿真和对比.仿真结果表明:提出的二维非递归FIR滤波器设计方法充分利用了系数矩阵的冗余信息,保留了现有算法的最小逻辑深度特性,同时可以进一步节省中间加法器个数;相比于现有的一维非递归算法,本算法可节省10.05%(12 bit量化)和7.21%(16 bit量化)的加法器个数;在低阶滤波器的设计中,加法器使用量降低到了传统CSD表示法的30%左右,从逻辑深度和加法器个数两方面都超越了已发表的递归和非递归滤波器设计方法.

Two-dimensional non-recursive design method of low-cost FIR filter

To reduce the overall hardware cost as well as improve the synthesizability of finite impulse response (FIR) filter, a two-dimensional non-recursive optimization algorithm based on coefficient matrix was proposed and simulated. Firstly, the existing digital filter optimization algorithms were investigated, and the advantages and shortcomings of these algorithms were compared and analyzed. Then, efforts were made to optimize the existing one-dimensional non-recursive algorithm. By extracting the redundant terms of one-dimensional non-recursive optimization algorithm, a novel two-dimensional non-recursive FIR optimization method with low computing complexity was obtained. Finally, multiple groups of filters were generated to simulate and compare the performance between the proposed algorithm and one-dimensional non-recursive algorithm as well as the existing recursive algorithms. Simulation results show that the two-dimensional non-recursive FIR filter design method proposed in this paper makes full use of the redundant information of the coefficient matrix, keeps the character of minimum logic depth, and meanwhile reduces logic adder number. Compared with the existing one-dimensional non-recursive algorithm, this algorithm saved logic adder by 10.05% (12 bit quantization) and 7.21% (16 bit quantization). In the design of low-order filter, the adder cost was reduced to 30% of the conventional CSD representation, which outperforms the existing recursive and non-recursive filter design methods in terms of logic depth and adder number.