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Linear equivalence of certain BRM shift-register sequences |
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| Authors: | Chambers WG Jennings SM |
| Affiliation: | Westfield College, University of London, Mathematics Department, London, UK; |
| Abstract: | A theorem given by Albert is used to show that if a shift register of length m is used to clock another shift register of length n through a binary rate-multiplier, then it can easily be arranged that the output has a linear equivalence of (2m ? 1)n and a period of (2m ? 1)(2n ? 1). |
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