Investigation of the characteristics of GIDL current in 90nm CMOS technology

A specially designed experiment is performed for investigating gate-induced drain leakage (GIDL) current in 90nm CMOS technology using lightly-doped drain (LDD) NMOSFET. This paper shows that the drain bias $V_{\rm D}$ has a strong effect on GIDL current as compared with the gate bias $V_{\rm G}$ at the same drain--gate voltage $V_{\rm DG}$. It is found that the difference between $I_{\rm D}$ in the off-state $I_{\rm D}-V_{\rm G}$ characteristics and the corresponding one in the off-state $I_{\rm D}-V_{\rm D}$ characteristics, which is defined as $I_{\rm DIFF}$, versus $V_{\rm DG}$ shows a peak. The difference between the influences of $V_{\rm D}$ and $V_{\rm G}$ on GIDL current is shown quantitatively by $I_{\rm DIFF}$, especially in 90nm scale. The difference is due to different hole tunnellings. Furthermore, the maximum $I_{\rm DIFF }$($I_{\rm DIFF,MAX})$ varies linearly with $V_{\rm DG}$ in logarithmic coordinates and also $V_{\rm DG}$ at $I_{\rm DIFF,MAX}$ with $V_{\rm F}$ which is the characteristic voltage of $I_{\rm DIFF}$. The relations are studied and some related expressions are given.