Transmission electron microscopy characterization of the erbium silicide formation process using a Pt/Er stack on a silicon-on-insulator substrate |
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| Authors: | A &#;ASZCZ J K&#;TCKI J RATAJCZAK XIAOHUI TANG† & E DUBOIS‡ |
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| Affiliation: | Institute of Electron Technology, al. Lotników 32/46, 02-668 Warsaw, Poland; Microelectronics Laboratory (DIDE), Universite Catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium; IEMN/ISEN, UMRS CNRS 8520, Avenue Poincare, BP 69, 59652 Villeneuve d'Ascq Cedex, France |
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| Abstract: | Very thin erbium silicide layers have been used as source and drain contacts to n‐type Si in low Schottky barrier MOSFETs on silicon‐on‐insulator substrates. Erbium silicide is formed by a solid‐state reaction between the metal and silicon during annealing. The influence of annealing temperature (450 °C, 525 °C and 600 °C) on the formation of an erbium silicide layer in the Pt/Er/Si/SiO2/Si structure was analysed by means of cross‐sectional transmission electron microscopy. The Si grains/interlayer formed at the interface and the presence of Si grains within the Er‐related layer constitute proof that Si reacts with Er in the presence of a Pt top layer in the temperature range 450–600 °C. The process of silicide formation in the Pt/Er/Si structure differs from that in the Er/Si structure. At 600 °C, the Pt top layer vanishes and a (Pt–Er)Six system is formed. |
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| Keywords: | Annealing erbium silicide interface transmission electron microscopy |
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