| 集成电路互连线寄生电容提取的软件设计 |
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| 引用本文： | 薛金涛,冯勇,林海,王高峰.集成电路互连线寄生电容提取的软件设计[J].计算机工程与应用,2004,40(26):106-108. |
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| 作者姓名： | 薛金涛 冯勇 林海 王高峰 |
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| 作者单位： | 武汉大学软件工程国家重点实验室,武汉大学黄彰任信息技术研究所,武汉,430072 |
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| 基金项目： | 国家自然科学基金重大研究计划重点项目:互连线建模、仿真和综合(编号:90307017) |
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| 摘 要： | 论文提出了一个超大规模集成电路(VLSI)片上三维互连线寄生电容精确提取流程模型。文中研究了该提取流程中计算区域的自动划分问题,并对该流程各个模块进行了设计。
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| 关 键 词： | VLSI 互连线 电容提取 |
| 文章编号： | 1002-8331-(2004)26-0106-03 |
Software Design for Parasitic Capacitance Extraction of IC Interconnections |
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| Xue Jintao Feng Yong Lin Hai Wang Gaofeng.Software Design for Parasitic Capacitance Extraction of IC Interconnections[J].Computer Engineering and Applications,2004,40(26):106-108. |
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| Authors: | Xue Jintao Feng Yong Lin Hai Wang Gaofeng |
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| Abstract: | In this paper,an on-chip parasitic capacitanc e extraction model of VLSI interconnections has been presented which captures3D geometry from layout design and process technology information.An automatic pl anning of computa-tional region is discussed in detail and program modules of t he extraction flow have been designed. |
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| Keywords: | VLSI interconnections capa citance extraction |
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