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一种快速全差分CMOS运算放大器
引用本文:林武平,郭良权,李亮,黄召军.一种快速全差分CMOS运算放大器[J].电子与封装,2008,8(12):20-23.
作者姓名:林武平  郭良权  李亮  黄召军
作者单位:[1]江南大学,江苏无锡214122; [2]中国电子科技集团第58研究所,江苏无锡214000
摘    要:文章在CSMC0.5μm/5V硅CMOS工艺模型下,设计了一种用于电表计量芯片的全差分运算放大器。该运放采用两级结构,其中第一级为折叠式共源共栅结构,第二级为PMOS输出缓冲结构。文章采用开关电容技术实现共模反馈以稳定输出共模电压,跟传统方法相比,这将能降低芯片面积及降低功耗。采用HSPICE软件对该电路进行仿真,仿真结果表明在负载电容为2pF情况下,该运算放大器具有开环增益为84.7dB、单位增益带宽达44.8MHz、相位裕度为67°、闭环小信号建立时间为39ns。

关 键 词:全差分  折叠式共源共栅  共模反馈  CMOS

A High-Speed Fully Differential CMOS Op-Amp
LIN Wu-ping,GUO Liang-quan,LI Liang,HUANG Zhao-jun.A High-Speed Fully Differential CMOS Op-Amp[J].Electronics & Packaging,2008,8(12):20-23.
Authors:LIN Wu-ping  GUO Liang-quan  LI Liang  HUANG Zhao-jun
Affiliation:LIN Wu-ping, GUO Liang-quan, LI Liang, HUANG Zhao-jun (1.Jiangnan University, Wuxi 214122, China; 2.No.58 Research Institute of China Electronics Technology Group Corporation, Wuxi 214000, China)
Abstract:Based on CSMC 0.5μm/5V Si CMOS technology, a high-speed fully differential operational amplifier used in energy metering IC was designed. In this OPA a two-stage structure consisting of a folded cascade amplifier and a PMOS output-buffer was adopted.In order to output a stable common-mode, switched capacitor common-mode feedback technique is used. Compare to traditional technique ,it can reduce the chip area and power consumption. And it is simulated with HSPICE software, results show that with a 2pF capacitor load it has an open loop gain of 84.7dB ,a unit gain bandwidth of 44.8MHz, a phase margin of 67°, and the settling time is 39ns.
Keywords:CMOS
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