| 一种浮点乘法器的参数化设计 |
| |
| 引用本文： | 蒋华,袁红林,徐晨.一种浮点乘法器的参数化设计[J].太赫兹科学与电子信息学报,2006,4(5):337-341. |
| |
| 作者姓名： | 蒋华 袁红林 徐晨 |
| |
| 作者单位： | 1. 东南大学,集成电路学院,江苏,南京,210096;南通大学,电子信息学院,江苏,南通,226007
2. 南通大学,电子信息学院,江苏,南通,226007 |
| |
| 基金项目： | 上海市科委资助项目;南通大学校科研和校改项目 |
| |
| 摘 要： |
|
| 关 键 词： | 参数化设计 浮点乘法器 可重配置 IP核 |
| 文章编号： | 1672-2892(2006)05-0337-05 |
| 收稿时间： | 2006-06-22 |
| 修稿时间： | 2006-07-28 |
Design of a Parameterized Floating Point Multiplier |
| |
| JIANG Hu,YUAN Hong-lin,XU Chen.Design of a Parameterized Floating Point Multiplier[J].Journal of Terahertz Science and Electronic Information Technology,2006,4(5):337-341. |
| |
| Authors: | JIANG Hu YUAN Hong-lin XU Chen |
| |
| Affiliation: | 1. Institute of Integrated Circuit, Southeast University, Nanjing Jiangsu 210096, China; 2. Institute of Electronic and Information, Nantong University, Nantong Jiangsu 226007, China |
| |
| Abstract: | Parameterized IP of floating point multiplier design method based on Verilog HDL is discussed in this paper, and three kinds of parameters are picked out. A new design method of muhiplieation operation between two fractions is pointed out, radix 4 Booth algorithm is used to compress partial products and a hybrid structure is used to divide partial products into several parts for parallel computing. The results are outputted by a carrying leading adder. As a parameterized design example, a single precision floating point multiplier module is given, which is provided with four grades of pipeline and a clock enabling port, and is compatible with IEEE754 as well. The experimental result indicates that the Parameterized Floating Point Multiplier IP core is reeonfigurable and reusable. |
| |
| Keywords: | parameterized design floating point multiplier reeonfigurable IP core |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
| 点击此处可从《太赫兹科学与电子信息学报》浏览原始摘要信息 |
|
点击此处可从《太赫兹科学与电子信息学报》下载全文 |
|
