| 数字图像处理算法评估系统的硬件设计 |
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| 引用本文： | 张桂林,张留洋.数字图像处理算法评估系统的硬件设计[J].计算机与数字工程,2005,33(12):88-91. |
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| 作者姓名： | 张桂林 张留洋 |
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| 作者单位： | 华中科技大学图像所智能控制实验室,武汉,430074;华中科技大学图像所智能控制实验室,武汉,430074 |
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| 摘 要： | 为了能对不同的数字图像处理算法进行评估，采用了USB2．0总线技术传送数字图象数据到数字图像处理系统，在硬件设计上采用DSP＋FPGA来完成图像处理任务。整个系统具有处理能力强，重现性好，能完成各种图像处理算法评估。
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| 关 键 词： | USB2.0 DSP FPGA 管道流水线 |
| 收稿时间： | 2005-04-06 |
| 修稿时间： | 2005年4月6日 |
Design and Implementation of Digital Image Processing Algorithm Evaluation System Based on DSP + FPGA + USB2.0 Architecture |
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| Zhang Guilin,Zhang Liuyang.Design and Implementation of Digital Image Processing Algorithm Evaluation System Based on DSP + FPGA + USB2.0 Architecture[J].Computer and Digital Engineering,2005,33(12):88-91. |
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| Authors: | Zhang Guilin Zhang Liuyang |
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| Affiliation: | Lab for Intelligent Control, Institute for Pattern Recognition and Artificial Intelligence, HUST,Wuhan 430074 |
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| Abstract: | The real-time digital image processing system is presented based on DSP + FPGA +USB2.0 architecture.The system uses height-performance DSP(TMS320C6202B) to realize the real-time digital image process algorithm,in the same time uses large-scale programmable logical array CPLD to control logic and FPGA to preprocess the image.USB 2.0 interface supplies high frame data from PC to the image-processing module.Various digital image process algorithms are realized in the field programmable gate array chip.The whole system is digital that is superior than the analog video signal.It proves to be reliable and effective for the request of system basically. |
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| Keywords: | USB2 0 DSP FPGA Pipeline |
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