一种超低功耗、容错的静态随机存储器设计

为了减轻辐射环境中静态随机存储器（SRAM）受单粒子翻转（SEU）的影响以及解决低功耗和稳定性的问题,采用TSMC 90nm工艺,设计了一款可应用于辐射环境中的超低功耗容错静态随机存储器。该SRAM基于双互锁存储单元（DICE）结构,以同步逻辑实现并具有1KB（1K×8b）的容量,每根位线上有128个标准存储单元,同时具有抗SEU特性,提高并保持了SRAM在亚阈值状态下的低功耗以及工作的稳定性。介绍了这种SRAM存储单元的电路设计及其功能仿真,当电源电压VDD为0.3V时,该SRAM工作频率最大可达到2.7MHz,此时功耗仅为0.35μW;而当VDD为1V时,最大工作频率为58.2MHz,功耗为83.22μW。

Design of ultralow-power fault-tolerant SRAM

To mitigate the effect of single-event upset(SEU) on SRAM,and realize the low power and high stability in the radiation environment,an ultra low-power fault-tolerant SRAM applied to the radiation environment was designed with TSMC 90 nm process technology.It is based on dual interlocked storage cell(DICE),implemented by synchronous logic,and has a capacity of 1K×8 bits,in which 128 storage cells are attached to each bit-line and has the ability immune to SEU.All the characteristics mentioned above improve the stability and also maintain the low power characteristic of SRAM in the sub-threshold status.In this paper,the circuit design of SRAM memory cell and function simulation are described.When VDD=0.3 V,the operation frequency of SRAM is up to 2.7 MHz and its power dissipation is only 0.35 μW;but when VDD=1 V,its maximum operation frequency is 58.2 MHz and its power dissipation is 83.22 μW.