Architecture Design of a Variable Length Instruction Set VLIW DSP |
| |
Authors: | SHEN Zheng HE Hu YANG Xu JIA Di SUN Yihe |
| |
Affiliation: | aTsinghua National Laboratory of Information and Technology, Institute of Microelectronics, Tsinghua University, Beijing 100084, China |
| |
Abstract: | The cost of the central register file and the size of the program code limit the scalability of very long instruction word (VLIW) processors with increasing numbers of functional units. This paper presents the architectural design of a six-way VLIW digital signal processor (DSP) with clustered register files. The architecture uses a variable length instruction set and supports dynamic instruction dispatching. The one-level memory system architecture of the processor includes 16-KB instruction and data caches and 16-KB instruction and data on-chip RAM. A compiler based on the Open64 was developed for the system. Evaluations show that the processor is suitable for high performance applications with a high code density and small program code size. |
| |
Keywords: | digital signal processor (DSP) very long instruction word (VLIW) variable length instruction set clustered register file |
本文献已被 CNKI 万方数据 ScienceDirect 等数据库收录! |