DSP与FPGA的SRIO互连设计

在DSP+FPGA的高速图像处理系统中,针对系统数据量大、运算复杂的特点,提出了一种基于SRIO协议的DSP与FPGA处理器互连,并进一步使用FPGA中的MPMC控制器连接DDR2SDRAM,实现了图像处理系统内部处理器的共享存储。该方法通过在DSP和FPGA上编程,实现了SRIO协议中的存储器映射I/O事务(LSU)方式的传输,处理器之间通过SRIO接口传输的数据速率达到3.125Gb/s。实验结果表明,该方法有效地实现了处理器之间数据稳定可靠的传输,使系统内的数据交换灵活快捷,提高了DSP的协处理能力,很好地满足了处理系统实时性的需求。

Interconnect between DSP and FPGA Based on SRIO Protocol

For the large data amount and computing complexity of the high-speed image processing system with the DSP+FPGA structure, an interconnect between DSP and FPGA processors is put forword based on SRIO protocol, and MPMC is used to implement shared storage of the internal processors. By programming on both DSP and FPGA processors, transactions in the direct I/O module are finally achieved inSRIO protocol. The interface can transfer data at the speed up to 3.125Gbps. Experimental results show the method can provide stable and reliable data transmissons between processors, realizing flexible and efficient data exchange within system.