| 单通道8bit1.4GS/s折叠内插ADC |
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| 引用本文： | 张有涛,李晓鹏,张敏,刘奡,钱峰,陈辰.单通道8bit1.4GS/s折叠内插ADC[J].固体电子学研究与进展,2011,31(4):393-397. |
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| 作者姓名： | 张有涛 李晓鹏 张敏 刘奡 钱峰 陈辰 |
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| 作者单位： | 南京电子器件研究所,微波毫米波单片集成和模块电路重点实验室,南京,210016 |
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| 摘 要： | 基于0.18 μm CMOS工艺设计并实现了一种8 bit 1.4 GS/s ADC.芯片采用多级级联折叠内插结构降低集成度,片内实现了电阻失调平均和数字辅助失调校准.测试结果表明,ADC在1.4GHz采样率下,有效位达6.4bit,功耗小于480 mW.文章所提的综合校准方法能够有效提高ADC的静态和动态性能,显示出...
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| 关 键 词： | 模数转换器(ADC) 失调校准 折叠内插 |
A Single Channel 8 bit 1.4 GS/s Folding and Interpolation ADC |
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| ZHANG Youtao,LI Xiaopeng,ZHANG Min,LIU Ao,QIAN Feng,CHEN Cheng.A Single Channel 8 bit 1.4 GS/s Folding and Interpolation ADC[J].Research & Progress of Solid State Electronics,2011,31(4):393-397. |
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| Authors: | ZHANG Youtao LI Xiaopeng ZHANG Min LIU Ao QIAN Feng CHEN Cheng |
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| Affiliation: | ZHANG Youtao LI Xiaopeng ZHANG Min LIU Ao QIAN Feng CHEN Cheng(Science and Technology on Monolithic Integrated Circuits and Modules Laboratory,Nanjing Electronic Devices Institute,Nanjing,210016,CHN) |
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| Abstract: | A 1.4 GS/s 8 bit ADC is demonstrated in 0.18 μm CMOS.The chip realizes cascade folding and interpolation with resistive averaging and digital calibration.Test results show that the ENOB could be 6.4 bit with 480 mW power dissipation while operating at 1.4 GS/s.The proposed effective calibration methods could improve the static and dynamic performance of ADC. |
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| Keywords: | analog-to-digital conversion offset calibration folding and interpolation |
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