Impact of gate poly doping and oxide thickness on the N- and PBTI in MOSFETs |
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| Authors: | Gregor Pobegen Thomas Aichinger Tibor Grasser Michael Nelhiebel |
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| Affiliation: | 1. KAI (Kompetenzzentrum für Automobil und Industrie-Elektronik), Europastraße 8, A-9524 Villach, Austria;2. The Pennsylvania State University, 101 Earth Engineering Science Building, University Park, PA 16802, USA;3. Institute for Microelectronics, Technical University Vienna, Gußhausstraße 27-29/E360, A-1040 Vienna, Austria;4. Infineon Technologies Austria AG, Siemensstraße 2, A-9500 Villach, Austria;1. Department of Electronics & Communication Engineering, School of Electrical and Electronics Engineering, SASTRA University, Thanjavur 613 401, India;2. Center for Advanced Research, Mahendra Engineering College, Mallasamudram 637 503, India;3. Department of Mathematics, SASTRA University, Thanjavur 613 401, India;1. Department of Studies in Physics, University of Mysore, Manasagangotri, Mysore 570006, India;2. Department of PG Studies in Physics, JSS College, Ooty Road, Mysore 570025, India;3. IUC-DAE CSR, Kolkota 700098, India;1. Faculty of Electrical, Biomedical and Mechatronics Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran;2. Department of Engineering Sciences, Faculty of Technology and Engineering, East of Guilan, University of Guilan, Rudsar-Vajargah, Iran;1. SUNY College of Nanoscale Science and Engineering, Albany, NY 12203, USA;2. Fermi National Accelerator Laboratory, Batavia, IL, 60510, USA |
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| Abstract: | We study n- and pMOS devices with 3.2–30 nm thick SiON or SiO2 gate dielectrics and n++ or p++ doped polysilicon gates to identify the type and energetic location of defects created through bias temperature stress. The results clearly indicate a dependence of the type of BTS induced defects on the stress polarity and the gate poly doping. If holes are provided from the p++ poly gate and the gate dielectric is sufficiently thin, NBTI-type donor-like defects may occur even under positive bias stress conditions. For devices with sufficiently thick dielectrics or n++ poly gated devices, holes are absent during PBTI stress and acceptor-like defects are created. |
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