用于Sigma—DeltaADC的数字抽取滤波器研究

该文提出了一种对数字抽取滤波器的参数进行自动优化设计的方案。针对降低数字抽取滤波器的面积和功耗，对确定合适的CIC抽取滤波器的级联数目和抽取因子以及半带滤波器的级联数目和阶数进行了讨论和分析。采用上述方案，实现了一个256倍的降频，输入信号采样频率为512kHz，输出信号频率为2kHz，输出信号的信噪比（SNR）为110dB的数字抽取滤波器。最后用Simulink软件进行了仿真验证。

Study on the Digital Decimation Filter Used for Sigma-Delta ADC

This paper proposes a scheme that is able to automatically achieve the optimal design for determining the parameters of a digital decimation filter. In allusion to the minimizing of area and power dissipation of the digital decimation filter, it discusses and analyses the problem of how to determine the cascading number and decimation factors of the CIC decimation filter and the cas- cading number as well as order of the Half-band filter. A digital decimation filter with the down-sampling ratio of 256 times, input signal sampling frequency of 512kHz, output signal frequency of 2kHz, output signal＇s SNR of ll0dB has been realized by using above-mentioned scheme. At the last, it is simulated and verified by means of Simulink software.