Optimization of a Hetero-Structure Vertical Tunnel FET for Enhanced Electrical Performance and Effects of Temperature Variation on RF/Linearity Parameters |
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| Authors: | Vanlalawmpuia K Bhowmick Brinda |
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| Affiliation: | 1.Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Assam, 788010, India
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| Abstract: | Silicon - A new hetero-structure vertical tunnel field effect transistor is proposed and investigated using Sentaurus Technology Computer-aided Design simulation. Since the direction of the gate... |
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