| 针对FPGA优化的高分辨率时间数字转换阵列电路 |
| |
| 引用本文： | 杨洋,阮爱武,廖永波,吴文杰. 针对FPGA优化的高分辨率时间数字转换阵列电路[J]. 电子技术应用, 2011, 37(2): 42-45 |
| |
| 作者姓名： | 杨洋 阮爱武 廖永波 吴文杰 |
| |
| 作者单位： | 电子科技大学电子薄膜与集成器件国家重点实验室VLSI设计中心,四川,成都,610054 |
| |
| 摘 要： | 介绍一种针对FPGA优化的时间数字转换阵列电路.利用FPGA片上锁相环对全局时钟进行倍频与移相,通过时钟状态译码的方法解决了FPGA中延迟的不确定性问题,完成时间数字转换的功能.在Altera公司的FPGA上验证表明,本时间数字转换阵列可达1.73 ns的时间分辨率.转换阵列具有占用资源少,可重用性高,可以作为IP核方...
|
| 关 键 词： | 时间数字转换 现场可编程门阵列 锁相环 状态译码 |
An FPGA-optimized high resolution time-to-digital converter array |
| |
| Yang Yang,Ruan Aiwu,Liao Yongbo,Wu Wenjie. An FPGA-optimized high resolution time-to-digital converter array[J]. Application of Electronic Technique, 2011, 37(2): 42-45 |
| |
| Authors: | Yang Yang Ruan Aiwu Liao Yongbo Wu Wenjie |
| |
| Affiliation: | Yang Yang,Ruan Aiwu,Liao Yongbo,Wu Wenjie(VLSI Design Center,State Key Lab of Electronic Thin Films and Integrated Devices,University of Electronic Science and Technology,Chengdu 610054,China) |
| |
| Abstract: | An FPGA-optimized high resolution time-to-digital converter array is proposed.In this design,we adapt the on-chip PLL as the frequency double circuit and the clock phase shifter.We use the method of clock state decoding to solve the delay uncertainty for FPGA,thereby fulfill the time to digital convert.The circuit has been implemented via FPGA produced by Altera Corp.The result shows that the time resolution is 1.73 ns.It enjoys the advantages of less resource usage,high reusability and easy implantation as... |
| |
| Keywords: | time-to-digital converter FPGA PLL state decoding |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
|
