大数模乘脉动阵列的FPGA细粒度映射实现

通过分析FPGA可配置逻辑块的细致结构,提出了一种基于FPGA的细粒度映射方法,并使用该方法高效实现了大数模乘脉动阵列.在保持高速计算特点的同时,将模乘脉动阵列的资源消耗降低为原来的三分之一.在低成本的20万门级FPGA器件中即可实现1024位模乘器.该实现每秒可进行20次RSA签名.如果换用高性能FPGA,签名速度更可提高至每秒40次.

FPGA Implementation of Systolic Array for Modular Multiplication Using a Fine-grained Approach

A fine-grained mapping approach is proposed according to the analysis of the detailed configurable logic block structure of FPGA device, and it is applied to the design of a systolic array for modular multiplication based on FPGA. Without performance losses, the logic resources consumed by the systolic array are reduced to one-third of its original requirement. By exploiting this approach, it's possible to implement a 1024-bit modular multiplier on a 200K gate low-cost FPGA, which can perform 20 1024-bit RSA signature operations per second. Implemented on a high-end FPGA, the modular multiplier can obtain a performance up to 40 signature operations per second.