片上多处理器的层次化高速测试和验证技术

片上多处理器的体系结构具有高效、低功耗的特点,但由于整体逻辑规模较大,且存储系统有一致性的要求,因此其模拟器测试和验证的计算量大、复杂度高,整体采用传统的形式化测试方法测试速度慢.运用分隔测试技术可以在测试过程中降低整体计算的复杂度,将使用传统测试方法不能测试的复杂系统测试简单化;利用随机程序生成技术可以减少测试人员编写测试程序的时间并加速发现系统的错误,并行测试技术可以快速低功耗检验片上多处理器存储器系统的功能并具有良好的可扩充性.将上述测试方法集成在片上多处理器的测试中,能够对整体的计算量进行合理的分割和并行化,迅速定位整个系统的错误,大大缩减所需要的测试时间,降低了测试人员的工作量,提高测试结果的覆盖率和可信性.

Hierarchical high speed testing and verification of chip-multiprocessors

CMP(Chip-Multi-Processor) is a high performance architecture with low power consumption.As the scale of the chip's logic is huge,and all parts of the memory system must be reliable,verification and testing of a CMP system is complicated and time consuming.The speed of testing using traditional methods of verification will be very slow.Breaking the testing process into discrete segments can reduce complexity and the computing workload,saving significant time.(Constrained random program generation,CRTPG)testing also reduces the work of the tester and finds bugs rapidly.Parallel testing and verification allows completion of testing in a shorter time with low power consumption and good scalability.Integrating all these methods in CMP testing can effectively share the workload of testing through effective parallelism,find bugs and mistakes quickly,reduce the time needed for testing and verification work and improve the coverage ratio of testing and thus,the reliability of the whole system.