一款多核处理器FPGA验证平台的设计与实现

高性能处理器设计日趋复杂，为了缩短验证周期，降低研制风险通常需要在流片之前进行基于现场可编程门阵列(field programmable gate-array, FPGA)原型验证平台的软硬件协同验证.随着处理器多核化的发展，FPGA原型验证平台的实现变得越来越具有挑战性.介绍了一款高性能多核微处理器FPGA验证平台的设计与实现方法，详细阐述了该FPGA验证平台采用的母板/子板总体架构、分片策略、时分复用实现技术及I/O接口实现方法.该平台具有良好的可扩展性，能够方便灵活地实现目标芯片在各种规模和配置下的FPGA验证，用于在流片前对目标芯片进行功能正确性验证和性能评估.经过该FPGA平台验证的目标芯片，首次流片返回的芯片能成功运行操作系统和各种应用程序，实现了一次流片成功的目标.最后对该FPGA验证平台的应用前景进行了分析总结.

Design and Implementation of FPGA Verification Platform for Multi-core Processor

As the design of high performance microprocessor becomes more and more complicated, the hardware-software co-verification, which is based on the FPGA (field programmable gate-array) prototyping verification platform, is usually used before tape-out. The use of FPGA platform is aimed to shorten the period of verification and reduce the risk of manufacture. With the developing of multi-core microprocessor, the implement of FPGA prototyping verification platform becomes more and more complex. Firstly, the paper introduces how to design and implement the FPGA prototyping verification platform for a high-performance multi-core microprocessor. Secondly, the paper describes the details about the construction of the FPGA platform, including strategy of FPGA partitioning, time division multiplexing communication, and implement of I/O interfaces. The FPGA platform is constructed by several mother boards and daughter boards, so it is adaptable for different periods of chip verification by changing the scale. This FPGA verification platform is scalable and flexible, and contributes a lot to the function correctness verification and performance evaluation of the target design. As a result, the success of the FPGA verification efforts underscored by first prototype chips which can boot operating system and test lots of application programs successfully. In the end, the paper also analyses the application prospect of this FPGA prototyping verification platform.