| 基于VHDL实现单精度浮点数的加／减法运算 |
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| 引用本文： | 覃霖,曾超.基于VHDL实现单精度浮点数的加／减法运算[J].电子工程师,2008,34(7):52-55. |
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| 作者姓名： | 覃霖 曾超 |
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| 作者单位： | 中国工程物理研究院电子工程研究所,四川省绵阳市,621900 |
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| 摘 要： | 研究了单精度浮点数加／减法的结构及其设计方法，并在Aldec公司的Active—HDL软件环境下，采用VHDL语言进行设计，并进行了仿真验证，计算精度可以达到10^-7。
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| 关 键 词： | 单精度浮点数 加/减法 VHDL FPGA |
Implementation of Adder or Subtraction of Float-point Number with Single Precision Based on VHDL |
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| QIN Lin,ZENG Chao.Implementation of Adder or Subtraction of Float-point Number with Single Precision Based on VHDL[J].Electronic Engineer,2008,34(7):52-55. |
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| Authors: | QIN Lin ZENG Chao |
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| Affiliation: | (Institute of Electronic Engineering, China Academy of Engineering Physics, Mianyang 621900, China) |
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| Abstract: | The structure and design of adder or subtraction of float-point number with single precision are studied under the Active-HDL software environment of the Aldec company. It is designed and simulated with VHDL, and the precision can reach 10 ^-7 . |
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| Keywords: | VHDL FPGA |
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