基于FPGA软件/硬件协同设计模式

可重构的计算机系统利用现场可编程门整列（FPGA）加快那些在CPU中运行过于缓慢计算的速度。在CPU中运行的软件用来重构FPGA芯片让芯片能够根据系统的需要运行特定的运算。这些系统一般使用消息传递机制来实现软件（运行在CPU和FPGA中）和硬件之间的通信。但是有一个缺点软件需要被写在一个特定的消息传递模式中。文章提出了一个新的轻便的软件和可重构硬件之间的接口。软件端能使用常规方法调用进行复杂计算,这些调用能被拦截和翻译成硬件消息。同样的,在硬件端能够使用软件的方法。这种接口不仅让实现新JAVA/FPGA协同设计变得简单,更重要的是加快了Java程序的运行速度。

A Coordinated Design Mode Based on FPGA Software/Hardware

Reconfigurable computing systems use a field programmable gate array （FPGA） to accelerate some computa- tions which execute too slowly on the central processing unit （CPU）. The software which runs on the CPU can configure the FPGA so that it can perform a certain computation, according to the needs of the system. These systems generally use message-passing for communication between the software （which runs on the CPU） and the hardware （FPGA）. This has the disadvantage that the software needs to be written in a specific message-passing style. We propose a new portable and transpar- ant interface between software（more specifically Java） and reconfigurable hardware. The software side can start complex computations using regular method calls, which can be intercepted and translated to hardware messages. Likewise, the hard- ware side can start methods in software. This interface makes it easy to implement new Java/FPGA co-designs, but also to accelerate existing Java applications.