| 基于FPGA的数字频率合成器设计与实现 |
| |
| 引用本文： | 贾伟伟,李美凤. 基于FPGA的数字频率合成器设计与实现[J]. 山西电子技术, 2012, 0(2): 14-15 |
| |
| 作者姓名： | 贾伟伟 李美凤 |
| |
| 作者单位： | 徐州工业职业技术学院,江苏徐州221140 |
| |
| 摘 要： | 为了产生稳定激励信号的目的,采用Verilog硬件语言在FPGA上实现了数字频率合成器的设计,该设计包括累加器、波形存储器、AD转换、低通滤波器等;对累加器、波形存储器都进行了仿真,并下载到FPGA中,经A/D转换,滤波,获得了稳定的正弦激励信号。本设计只实现了正弦信号设计,通过对波形存储器数据改变,可以实现任意波形的输出。
|
| 关 键 词： | FPGA 数字频率合成器 信号发生器 VerilogHDL |
The Design and Implementation of Direct Digital Synthesizer Based on FPGA |
| |
| Jia Wei-wei,Li Mei-feng. The Design and Implementation of Direct Digital Synthesizer Based on FPGA[J]. Shanxi Electronic Technology, 2012, 0(2): 14-15 |
| |
| Authors: | Jia Wei-wei Li Mei-feng |
| |
| Affiliation: | (Xuzhou College of Industrial Technology,Xuzhou Jiangsu 221140,China) |
| |
| Abstract: | In order to generate the purpose of stable excitation signal,the paper realizes the digital frequency synthesizer based on FPGA with Verilog.The design includes accumulators,waveform memory,AD transform,low pass filter components etc.;Accumulators,waveform memory are simulated and download to FPGA,passed through AD transform,filter to gain a stable sine excitation signal.This design only realizes the sine signal design;and the arbitrary waveforms would be realized through changing the waveform memory data. |
| |
| Keywords: | FPGA direct digital synthesizer signal generator verilogHDL |
| 本文献已被 维普 等数据库收录！ |
|
