基于CORDIC算法的高速正余弦函数实现架构

坐标旋转数字计算机算法（Coordinates Rotation Digital Computer （CORDIC） Algorithm），其硬件结构实现简单，可以在硬件系统中实现包括乘、除、各种三角函数、自然对数和平方根在内的初等函数；针对图像处理对计算速度要求高的特点，本文采用了多级流水线的实现架构，可以明显提高CORDIC电路的工作频率；为了进一步地减少各级流水线的计算时延，电路中采用了运算速度较快的BKA加法器。基于Altera公司的FPGA（EP2C5F256C7）芯片的CORDIC算法架构综合，使其能够工作在188．38MHz的最高时钟频率。仿真结果表明本文提出的CORDIC架构能高速正确地实现CORDIC算法。

The Realizing Architecture of High-speed Sine and Cosine Function Based on CORDIC Algorithm

CORDIC Algorithm, i.e. Coordinates Rotation Digital Computer Algorithm, its hardware architecture is easy to realize, and the elementary functions, including multiplying, dividing, various kinds of trigonometric function, natural logarithm and square root, can be realized in the hardware system. In this paper, in allusion to the characteristics of requiring a high calculating speed in application of image processing, the realizing architecture of multistage pipelining is adopted, thus the operating frequency of CORDIC circuit can significantly be increased. In order to further decrease the calculating delay times of the all stages of pipelining, the Brent-Kung Adder with the faster arithmetic speed is adopted in the circuit. The synthesis of CORDIC Algorithm architecture based on the FPGA chip （EP2C5F256C7）made by Ahera Company allows the architecture to work at the maximum clock rate of 188.38MHz. The simulation result shows that the proposed CORDIC architecture can correctly realize the CORDIC Algorithm at the high speed.