Low-power logic circuit and SRAM cell applications with silicon on depletion Layer CMOS (SODEL CMOS) technology |
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Authors: | Inaba S Nagano H Miyano K Mizushima I Okayama Y Nakauchi T Ishimaru K Ishiuchi H |
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Affiliation: | Process & Manuf. Eng. Center, Toshiba Corp. Semicond. Co., Yokohama, Japan; |
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Abstract: | In this paper, the switching performance of Silicon on Depletion Layer CMOS (SODEL CMOS) is investigated with a view to realizing high-speed and low-power CMOS applications. Thanks to smaller parasitic capacitance, the propagation delay time (/spl tau//sub pd/) in SODEL CMOS has been improved by up to 25% compared to that of conventional bulk CMOS in five stacked nFET inverters at the same V/sub dd/. It is also confirmed that about 30% better power-delay product can be realized at the same /spl tau//sub pd/ with reduced V/sub dd/ in SODEL CMOS. In SRAM cell applications, SODEL CMOS shows high Static Noise Margin (SNM) of /spl sim/95 mV at V/sub dd/=0.6 V. Smaller bitline delay is expected and confirmed in SODEL CMOS SRAM by SPICE simulations. Latch-up immunity for /spl alpha/-particle irradiation in SODEL CMOS was also found to be comparable to that of conventional bulk CMOS. Therefore, SODEL CMOS device and circuit technology is expected to provide a better solution for low-power system-on-a-chip (SoC). |
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