电流型CMOS脉冲D触发器设计

该文根据脉冲触发器的设计要求，结合阈算术代数系统，提出一种电流型CMOS脉冲D触发器的通用结构，用于二值及多值电流型CMOS脉冲触发器的设计，并可方便地应用于单边沿和双边沿触发。在此结构的基础上设计了电流型CMOS二值、三值以及四值脉冲D触发器。采用TSMC 180 nm CMOS工艺参数对所设计的电路进行HSPICE模拟后表明所设计的电路具有正确的逻辑功能和良好的瞬态特性，且较以往文献提出的电流型D触发器，优化了触发器的建立时间和保持时间，二值和四值触发器最差最小D-Q延时比相关文献的主从触发器降低了59.67%和54.99%，比相关文献的边沿触发器降低了4.62%以上，所用晶体管数也相对减少，具有更简单的结构以及更高的电路性能。

Design of Current-mode CMOS Pulse-triggered D Flip-Flops

With the requirements of pulsed-triggered Flip-Flop and the threshold-arithmetic algebraic system, a novel universal structure of current-mode CMOS pulsed-triggered D Flip-Flop is proposed for binary and multi-valued current-mode CMOS pulsed-triggered D Flip-Flops design. Based on the proposed structure, a Binary Current-Mode CMOS pulse-triggered D Flip-Flop (BCMPDFF), a Ternary Current-Mode CMOS Pulse-triggered D Flip-Flop (TCMPDFF) and a Quaternary Current-Mode CMOS Pulse-triggered D Flip-Flop (QCMPDFF) are designed, respectively, and the designed Flip-Flops can be easily incorporated into single and double edge-triggered design. The HSPICE simulation using TSMC 180 nm CMOS technology show that the designed D Flip-Flops based on the proposed universal structure have the correct logic function. The setup time and hold time of the designed Flip-Flops are optimalized, respectively. Comparing to the published current-mode CMOS master-slave D Flip-Flops, the worst minimum D-Q delay of BCMPDFF and QCMPDFF can be reduced by 56.97% and 54.99%, respectively, comparing to the published current-mode CMOS edge-triggered D Flip-Flops, the worst minimum D-Q delay can be reduced by at least 4.26%. The designed Flip-Flops have the advantage of fewer transistors, relatively simpler structure and higher performance.