| 基于VHDL的全数字单稳态电路研究 |
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| 引用本文： | 赵世平,张玉华. 基于VHDL的全数字单稳态电路研究[J]. 电力学报, 2005, 20(4): 336-337,358 |
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| 作者姓名： | 赵世平 张玉华 |
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| 作者单位： | 山西大学工程学院,山西,太原,030013 |
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| 摘 要： | 对在大规模可编程逻辑器件中实现单稳态电路的方法和程序设计进行了探讨,给出了实现不可重触发和可重触发功能的单稳态电路的VHDL程序,并对所有程序进行了计算机仿真。分析了影响全数字单稳态电路定时精度的原因及解决方法。
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| 关 键 词： | 可编程逻辑器件 单稳态触发器 VHDL 可重触发 |
| 文章编号： | 1005-6548（2005）04-0336-02 |
| 收稿时间： | 2005-10-12 |
| 修稿时间： | 2005-10-122005-10-28 |
A Research on All Digital Monostable Circuit Based on VHDL |
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| ZHAO Shi-ping,ZHANG Yu-hua. A Research on All Digital Monostable Circuit Based on VHDL[J]. Journal of Electric Power, 2005, 20(4): 336-337,358 |
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| Authors: | ZHAO Shi-ping ZHANG Yu-hua |
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| Affiliation: | Engineering College of Shanxi University,Taiyuan 030013,China |
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| Abstract: | With the large-scale programmable logic device(PLD), a method of making the digital monostable circuit work and the design of program are discussed in this paper.At the same time,the program based on VHDL about how to realize the functions of the nonretriggerable and retriggerabie monostable circuit is also given.Again,the simulation result proves it correctly.In addition,the reason for affecting the timing precision of the monostable circuit is analyzed and the solution of this problem is put forward. |
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| Keywords: | VHDL |
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