拉伸法测金属杨氏模量实验的改进

传统的拉伸法测金属杨氏模量实验、实验过程不够科学、实验仪器不便调节等缺点，方法和过程适当地进行完善，克服了以上缺点，存在着实验条件难以保证、实验方法不够完善、该文用游标卡尺对实验装置进行改进，并对实验提高了实验精度。     

一种应用于全数字锁相环的时间数字转换器设计

设计了一个应用于全数字锁相环的时间数字转换器(TDC).该时间数字转换器具有两种工作模式——粗量化和细量化.为了提高细量化模式的测量范围,TDC采用1-bit decision-select结构和游标门控环形振荡器(Vernier GRO)构成其两级量化单元.通过在Vernier GRO中使用一种新型结构的比较器,消除了用SR触发器做比较器时对测量范围的制约,也提高了GRO设计的灵活性.在TSMC 0.13μm工艺,1.2 V电源电压和40MHz采样速率下,仿真结果表明本设计的TDC在粗量化模式下具有不小于25ns的测量范围,在细量化模式下有效分辨率和测量范围分别为30ps,1.8ns.     

游标测距在全相参脉冲多普勒雷达中的应用

该文给出了游标测距在现代雷达中的一种应用方法。通过对游标测距原理的分析,得到了实现游标测距所需的雷达测量数据,即距离数据、基带I／Q数据和多普勒频率数据。最后通过理论分析证明,当这些数据的测量误差满足一定条件时,即可实现游标测距。     

可变磁通永磁游标电机设计及静态特性分析

为实现永磁电机在体积和槽数不增加情况下产生低速大转矩输出,将混合励磁概念引入永磁游标电机,提出了一种新型可变磁通永磁游标电机。通过将磁通调制极引入到电机定子齿以及在相邻磁通调制极间布置励磁绕组,实现了电机磁通可控,从而保证在增磁及弱磁过程中宽调速范围运行。分析了其工作原理,采用时步有限元方法计算了电磁特性,包括空载永磁磁链、空载感应电动势、齿槽转矩和输出转矩,对其增磁弱磁过程进行了分析。制作了一台1 kW样机;并对其静态特性进行了测试。结果表明该电机具有转矩密度大、齿槽转矩小、调速范围宽特点,适用于风力发电、电动汽车领域。     

On-Chip Multi-Giga Bit Cycle-to-Cycle Jitter Measurement Circuit

This paper presents an on-chip measurement circuit to measure multi-giga bit cycle-to-cycle jitter based on the vernier oscillator (VO), which is inherited from the famous vernier delay line. The calibration method is also given. The circuit adopts a differential digital controlled delay element, which makes the circuit flexible in adjusting the measurement resolution, and a highly sensitive phase capturer, which makes the circuit able to measure jitters in pico-second range. The parallel structure makes it possible to measure consecutive cycle-to-cycle jitters. The performance of the circuit was verified via simulation with SMIC 0.18 μm process. During simulation under the clock with the period of 750 ps, the error between the measured RMS jitter and the theoretical RMS jitter was just 2.79 ps. Monte Carlo analysis was also conducted. With more advanced technology, the circuit can work better. This new structure can be implemented in chips as a built-in self-test IP core for testing jitter of PLL or other clocks.     

弯管流量计现场检定关键参数测量方法

简要介绍几种弯管传感器重要参数弯径比的测量方法及其特点,经分析比较,提出弯管流量计现场检定可供选择的两种弯径比测量方法。通过随机抽查样件,同时用这两种弯径比测量方法进行检测,发现只有定弓高弦长法,适用于机加工传感器现场几何检定中关键参数弯径比的测量,其结果才是正确可靠的。     

On-Chip Built-in Jitter Measurement Circuit for PLL Based on Duty-Cycle Modulation Vernier Delay Line

Phase-locked loops (PLLs) are essential wherever a local event is synchronized with a periodic external event. They are utilized as on-chip clock frequency generators to synthesize a low skew and higher internal frequency clock from an external lower frequency signal and its characterization and measurement have recently been calling for more and more attention. In this paper, a built-in on-chip circuit for measuring jitter of PLL based on a duty cycle modulation vernier delay line is proposed and demonstrated. The circuit employs two delay lines to measure the timing difference and transform the difference signal into digital words. The vernier lines are composed of delay cells whose duty cycle can be adjusted by a feedback voltage. It enables the circuit to have a self calibration capability which eliminates the mismatch problem caused by the process variation.     

基于光学游标测量原理的平行光入射角度测量方法

为解决平行光入射角度精确测量时,很难同时实现高精度和大量程两方面的测量性能要求的问题,提出了一种基于光学游标测量原理的大量程条件下的高精度平行光入射角度测量方法及测量装置。基于该方法设计的测量装置,在±64°测量范围内,全量程测量精度优于0.02°。对测量装置的实验结果表明,实验结果与理论分析相吻合。该装置可以在航天、精密计量测试以及自动控制等领域实现对平行光入射角度的精密测量。     

基于游标法的高精度测频系统设计

为了有效地改善传统测频方法精度低、误差大的问题,提出了一种基于多周期分频段测量法与双游标法相结合的高精度测频方案。可对0.1 Hz—5 MHz范围内的频率信号进行测量。系统通过在Quartus II中用VHDL语言编写脉冲计数及控制模块,并在FPGA芯片内植入NIOS II软核处理器作为系统的控制核心,完成对惯导组件输出的频率信号进行测量。并将测量结果传至上位机进行处理和显示。实验结果表明,系统具有较高的测量精度。同时由于采用软核处理器,大大降低了成本,具有很好的实用价值。