Σ△微加速度计中基于脉宽调制的力反馈回路

针对微加速度计接口电路的sigma delta（ΣΔ）数字反馈系统,本文提出一种基于脉宽调制（PWM）的力反馈回路：利用模拟低通滤波器将PWM波解调成模拟输出信号,具有滤波和数模转换功能。首先建立了微加速度计ΣΔ闭环反馈系统的Simulink模型并进行了系统级仿真。之后采用Filter Solutions滤波器设计软件确定三阶低通巴特沃斯滤波器,并采用Pspice仿真软件进行电路级仿真。最后将制作的PCB版电路进行测试：PWM波通过力反馈回路能还原成高保真的模拟信号,输出信号和输入信号的频率相对误差小于0.36%,等效DAC分辨率为8位。试验表明,此方案结构简单、成本低,能以较低电路复杂度实现高精度的模拟信号输出。     

基于Σ-Δ调制技术的TWACS通信信号特征提取

针对双向工频自动通信系统(TwoWayAutomaticCommunicationSystem———TWACS)通信信号时域检测方法特征量少和抗干扰能力差,而时频分析方法数据处理复杂,装置成本高,提出了基于Σ-Δ增量调制技术提取TWACS通信信号的新方法.该方法在电网信号的调制区域将Σ-Δ调制器输出的1位数据流信息进行累加,将前后两抽样值的差值进行量化编码来代表连续信号所包含的信息,即采用增量调制的方式对相邻两个电网波形的位流和求差值来判断通信信号的有无,同时推导了有效的时域检测算法.对实际电网的测试表明,这种方案能够提取强干扰下电网中的调制信号,扩展了TWACS通信系统的应用范围.     

Design of a high-order single-loop Σ△ ADC followed by a decimator in 0.18μm CMOS technology

This work presents an oversampled high-order single-loop single-bit sigma–delta analog-to-digital converter followed by a multi-stage decimation filter.Design details and measurement results for the whole chip are presented for a TSMC 0.18μm CMOS implementation to achieve virtually ideal 16-b performance over a baseband of 640 kHz.The modulator in this work is a fully differential circuit that operates from a single 1.8 V power supply. With an oversampling ratio of 64 and a clock rate of 81.92 MHz,the modulator achieves a 94 dB dynamic range. The decimator achieves a pass-band ripple of less than 0.01 dB,a stop-band attenuation of 80 dB and a transition band from 640 to 740 kHz.The whole chip consumes only 56 mW for a 1.28 MHz output rate and occupies a die area of 1×2 mm^2.     

A high dynamic range analog-front-end IC for electrochemical amperometric and voltammetric sensors

A wide input range, compliant with electrochemical amperometric and voltammetric sensors analog-front-end (AFE) integrated circuit (IC) is proposed. The AFE employs current integrator (CI) and trans-impedance amplifier (TIA) to deal with the input current in the order of nA and μA separately, achieving the advantage of high dynamic range and high resolution. Input voltage is converted to current through a series of precise resistances, and detected by CI or TIA, which making the input voltage range is not limited by the power supply. An incremental sigma-delta ADC is employed to digitize the transferring signal, reducing the complexity and power dissipation. Compared to other alternatives, the AFE could handle current and voltage signals simultaneously, and input voltage range is not limited by power supply, showing high dynamic range and resolution. The AFE IC is fabricated in 0.18 μm 1P5M mixed-signal CMOS process, occupies an area of 3.2 mm×2 mm, the readout circuit has a dynamic range of 120 dB, consumes 4.2 mA.     

一种基于音频应用的∑△power DAC研究和实现

介绍了一种应用在音频系统的∑△power DAC。对整个∑△power DAC的设计进行了详细的介绍，实际的硬件用Synopsys工具进行了完整的电路设计、仿真和版图设计。在MP3中得到实际应用，音质效果良好。     

Current Operational Amplifier (COA): CMOS Realization and Active Compensation

A methodology for analysis and synthesis of lowpass sigma-delta () converters is presented in this paper. This method permits the synthesis of modulators employing continuous-time filters from discrete-time topologies. The analysis method is based on the discretization of a continuous-time model and using a discrete simulator, which is more efficient than an analog simulator. In our analysis approach, the influence of the sample and hold block and non-idealities of the feedback DAC can be systematically modeled by discrete-time systems. Finally, a realistic design of a second-order modulator with a compensation of the non-ideal behavior of the DAC is given. Moreover, simulation results show a good agreement with the theoretical predictions.     

Adaptive Correction of Errors in Residue Coupled MASH ΔΣ Modulators

MASH delta-sigma () modulators consist of a cascade of several lower order single-loop modulators. In an ideal cascade, the quantization error from all but the last stage are digitally canceled. The drawback with a cascaded design is the requirement of precise matching of contributions from different quantizers to cancel lower order quantization noise from intermediate delta-sigma stages. This paper presents a new, adaptive improvement to the residue coupled MASH delta sigma modulator. The adaptive corrections significantly reduce the sensitivity to analog imperfections. The result is a simple MASH delta-sigma modulator with high precision. Simulations of a 1-1 MASH circuit structure with errors and corrections are included to confirm the theory.     

The ΣΔ-BIST Method Applied to Analog Filters

This paper describes the -BIST method, defined as an analog BIST circuit in the context of mixed signal systems. The test procedure is based on the reuse of existing analog circuits configured as sigma-delta modulators in the analog domain. The test procedure reuses most of existing blocks in a mixed signal system, and thus has small area overhead. Test sensitivity is very high, detecting small component deviations. Moreover, the proposed test technique can be applied to continuous or sampled time circuits, and the test procedure can be developed in the field. The paper explains the method and presents practical results to validate the proposed approach.     

用于电池管理系统的Sigma-Delta ADC模型优化设计及研究

针对用于电池管理系统中数模转换器的高精度要求以及Sigma-Delta ADC的适用特点,提出了一种加入零点优化的单环三阶前馈调制器结构以及适用于本系统的低功耗数字滤波器模型,通过噪声传输函数设计三准则和信号频谱分析给出具体设计及仿真参数,经验证该模型达到系统所需16位有效分辨率要求且易于电路实现。     

改进的适用于GSM的单环过采样调制器

传统的前馈结构由于在量化器前存在复杂的加法器因而会造成性能受限。本文给出了一个改进的四阶一位过采样调制器, 它采用了简单的加法器和延时输入前馈通路,从而降低了调制器的时序需求同时实现低失真。调制器由0.35微米工艺流片,完成了92.8dB的信号噪声失真比和101dB的动态范围,信号带宽100kHz,在3.3V电源电压下,消耗8.6mW。本调制器的性能满足GSM系统的需求。