基于Multisim8的压控振荡电路仿真分析

介绍了Multisim8的仿真功能的特点，并通过实例说明了用Multisim8进行仿真分析的具体方法，简单介绍了如何设置参数和进行仿真操作。     

高频数字锁相环的研究

论文阐述了１００ＭＨｚ数字锁相环的设计过程，用１０ＭＨｚ晶体振荡器对１００ＭＨｚ数字压控振荡器进行锁相，使１００ＭＨｚ输出信号指标得到很大改善。论文还分析了各单元电路，关键点时域波形测试，频谱测试。     

A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX

This paper presents a low power and low phase noise CMOS integer-N frequency synthesizer based on the charge-pump Phase Locked Loop (PLL) topology. The frequency synthesizer can be used for IEEE 802.16 unlicensed band of WiMAX (World Interoperability for Microwave Access). The operation frequency of the proposed design is ranged from 5.13 to 5.22 GHz. The proposed Voltage-Controlled Oscillator (VCO) achieves low power consumption and low phase noise. The high speed divider is implemented by an optimal extended true single phase clock (E-TSPC) prescaler. It can achieve higher operating frequency and lower power consumption. A new frequency divider is also proposed to eliminate the hardware overhead of the S counter in the conventional programmable divider. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump, a low-pass loop filter, a VCO, and a frequency divider. The simulated phase noise of the proposed VCO is −121.6 dBc/Hz at 1 MHz offset from the carrier frequency. The proposed frequency synthesizer consumes 13.1 mW. The chip with an area of 1.048 × 1.076 mm² is fabricated in a TSMC 0.18 μm CMOS 1P6M technology process.     

连续型Δ∑调制器设计综述

Δ∑调制器作为数字转换器中重要的类型,以其较高精度及对CMOS工艺演进的更强适应性得到广泛应用.阐述了Δ∑调制器中连续型的Δ∑调制器的主要设计要点,介绍了国内外在连续型Δ∑调制器上的研究现状,并对相应设计方法进行分类总结.分析了连续Δ∑调制器的工作原理、系统结构、电路误差及模型,对其发展趋势以及面临的挑战进行了总结.结果说明合理地利用新工艺及新型积分器可以有效提高连续型Δ∑调制器的带宽及能效.     

A frame‐based EM‐simulation for design of LC oscillator with MoM capacitor banks

This article presents a simulation method for the design of a digitally controlled oscillator (DCO). Electromagnetic (EM) simulations are essential and inevitable for modern LC oscillator design. Although EM‐simulators provide high accuracy, the EM‐simulation time is very long when metal‐oxide‐metal (MoM) capacitors are present. The proposed frame‐based EM‐simulation can significantly reduce the EM‐simulation time even in the presence of MoM capacitors without influencing the accuracy. To verify the proposed method, a DCO was fabricated using a 55‐nm CMOS process. Measurements of the DCO are in good agreement with the frame‐based post‐layout simulation results. In addition, the DCO has good performances with a low power consumption of approximately 0.68 mW.     

数据通信系统中宽范围压控振荡器(VCO)电路设计

本文对数据无线电通信系统中的宽范围压控振荡器（VCO）电路进行了理论分析和实验研究。为该类电路的设计提供了必要的理论依据。     

4～8 GHz雷达载波产生的硬件电路设计

本文主要讨论的是如何产生4~8GHz雷达载波信号。首先,给出了电路设计的整体方案,对其工作原理进行了详细的说明。其次,对方案的主要部分进行了硬件电路设计,给出了详细的设计原理图。该电路设计主要是基于AD9854和压控振荡器基础上,以DSP为控制核心来实现的。该方法对其他波段雷达载波或雷达信号的产生同样具有重要的参考价值。     

基于DDS＋PLL频率合成器的设计与实现

本文介绍了一种针对某跳频通信系统频率合成器的设计方案。在ADS软件环境下进行设计及仿真,并对结果进行了系统分析。设计方案经测试,该频率合成器可以输出200～270MHz范围内的高精度频率信号,频率步进为25kHz,跳频时间小于200μs,技术指标均达到预期要求。能够满足VHF和UHF波段跳频系统的需求,具有较高的使用价值。     

A 4.8–6.8 GHz low phase noise LC VCO in 0.13‐µm CMOS technology

This letter presents a novel LC voltage controlled oscillator (VCO) supporting the high‐speed serial transmission standard of RapidIO in 0.13‐µm complementary metal‐oxide semiconductor technology. The low phase noise is achieved through several techniques including current source switching, parallel coupled negative transconductance cell, and varactor bias combination scheme. Measured results of proposed circuit show a low phase noise of ?120 dBc/Hz at 1 MHz offset from 6.25 GHz carrier and tuning range of 4.8 ~ 6.8 GHz (34.48%) while consuming 7.4 mW under the supply voltage of 1.2 V. Copyright © 2015 John Wiley & Sons, Ltd.     

一种应用于GNSS接收机常数环路带宽的小数频率合成器

提出了一种应用于手持式民用GNSS接收机常数环路带宽的小数频率合成器,并在0.13μm 1P6M 的CMOS工艺中实现。通过离散的工作区域,LC-VCO用简单的结构获得宽的调节范围和小的压控灵敏度。提出的杂散抑制技术来最小化由于鉴频鉴相器和电荷泵引入的相位偏移。当PLL输出频率改变或温度变化时,通过自动环路校正模块自适应调整电荷泵电流保持优化的环路带宽不变。测试结果显示,该频率合成器带内相位噪声小于-93dBc（10 kHz 频率偏移处）,杂散小于-70 dBc, 环路带宽变化小于?3%;在1V的电源供电下,整个合成器（不包括本振测试buffer）消耗4.5mA电流,面积为0.5mm2。