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Christian Schuberth Peter Singerl Michael E. Gadringer Holger Arthaber Andreas Wiesbauer Gottfried Magerl 《国际射频与微波计算机辅助工程杂志》2010,20(4):446-457
This article presents a switched‐mode transmitter architecture using a current mode class‐D (CMCD) amplifier. To achieve high average efficiency for a modulated signal the envelope of the complex baseband signal is transformed into pulses such that the CMCD amplifier is operated either at its peak efficiency or completely switched off. The CMCD amplifier has been designed based on single‐tone active harmonic load‐pull measurements to achieve a power‐added efficiency (PAE) of 61.5% with 25 W output power at 900 MHz using LDMOS FETs. Removing the losses of the demodulation filter and of the amplifier a 10% higher efficiency than in an ideal class‐B amplifier can be obtained for burst‐mode operation with a peak‐to‐average power ratio of 10 dB. © 2010 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2010. 相似文献
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1200V MR D-RESURF LDMOS与BCD兼容工艺研究 总被引:1,自引:0,他引:1
提出具有p埋层的1200V多区双RESURF(MR D-RESURF) LDMOS, 在单RESURF(S-RESURF)结构的n漂移区表面引入多个p掺杂区,并在源区下引入p埋层,二者的附加场调制器件原来的场,以改善其场分布;同时由于电荷补偿,提高了漂移区n型杂质的浓度,降低了导通电阻.开发1200V高压BCD(BJT,CMOS,DMOS)兼容工艺,在标准CMOS工艺的基础上增加pn结对通隔离,用于形成DMOS器件D-RESURF的p-top注入两步工序,实现了BJT,CMOS与高压DMOS器件的单片集成.应用此工艺研制出一种BCD单片集成的功率半桥驱动电路,其中LDMOS,nMOS,pMOS,npn的耐压分别为1210,43.8,-27和76V.结果表明,此兼容工艺适用于高压领域的电路设计中. 相似文献
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提出了一种带n型浮空埋层的超低比导通电阻的变k槽型LDMOS(TLDMOS)。新结构在漂移区内引入变介电常数(VK)的深槽结构和自驱动的U型p区,不仅可提高漂移区的掺杂浓度,还可优化体内电场分布。衬底中引入的n埋层在器件阻断时进一步调制漂移区的电场分布。同时,额外p衬底/n埋层结的引入提高了LDMOS的纵向耐压。导通时,由于集成低压电源施加于U型p区,在其周围产生的电子积累层使器件在不增加栅电荷的情况下显著降低了比导通电阻(Ron,sp)。仿真结果表明,与传统TLDMOS相比,在相同元胞尺寸下,新结构的击穿电压提高了59.3%,Ron,sp降低了86.3%。 相似文献
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LDMOS以其大功率、高线性度和高效率等优点得到广泛的应用.采用2-tone负载牵引法得到了LDMOS晶体管MRF18030的输入和输出阻抗.在对晶体管绝对稳定性分析的基础上,运用共轭匹配法设计出匹配网络,并将匹配网络转化为MOMENTUM元件运用在电路设计中,大大提高了设计的准确性.采用载波复幂级数法对PA的AM-AM和AM-PM非线性特性进行了准确计算,弥补了传统泰勒级数只能分析AM-AM的不足.得到了用来消除PA非线性的反载波复幂级数.根据所得反载波复幂级数,利用二极管非线性特性设计出一种新的结构简单、易于实现的预失真器,给出其准确的电路模型表达式,得到了幅值、角度等参数的精确值.ADS仿真结果表明,IMD3改善了27dB.最终,成功设计出大功率、高效率、高线性的LDMOS微波功率放大器. 相似文献
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本文提出了一种新型的复合多晶硅栅LDMOS结构.该结构引入栅工程的概念,将LDMOST的栅分为n型多晶硅栅和p型多晶硅栅两部分,从而提高器件电流驱动能力,抑制SCEs(short channel effects )和DIBL(drain-induced barrier lowering).通过求解二维泊松方程建立了复合多晶硅栅LDMOST的二维阈值电压解析模型.模型考虑了LDMOS沟道杂质浓度分布和复合栅功函数差的共同影响,具有较高的精度.与MEDICI数值模拟结果比较后,模型得以验证. 相似文献
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An LDMOS with nearly rectangular-shape safe operation area (SOA) and low specific on-resistance is proposed. By utilizing a split gate, an electron accumulation layer is formed near the surface of the n-drift region to improve current conduction capability during on-state operation. As a result, the specific on-resistance can be lowered down to 74.7 mΩ·cm2 for a 600 V device from simulation. Furthermore, under high-voltage and high-current conditions, electrons and holes flow as majority carriers in the n-drift region and p-type split gate, respectively. Due to charge compensation occurring between holes and electrons, the local electric field is reduced and impact ionization is weakened in the proposed device. Therefore, a higher on-state breakdown voltage at large VGS is obtained and snap-back is suppressed as well. 相似文献