DVB-T调制器外码编码器的FPGA设计

设计并实现了一种DVB—T调制器的外码编码器，着重介绍了码流自适应接口、能量扩散、RS编码器及卷积交织器的设计方法，该设计方案最终在Altera的FPGA上进行验证。     

Controlled elements for designing ciphers suitable to efficient VLSI implementation

This work considers the problem of increasing the performance of the ciphers based on Data-Dependent (DD) operations (DDO) for VLSI implementations. New minimum size primitives are proposed to design DDOs. Using advanced DDOs instead of DD permutations (DDP) in the DDP-based iterative ciphers Cobra-H64 and Cobra-H128 the number of rounds has been significantly reduced yielding enhancement of the “performance per cost” value and retaining security at the level of indistinguishability from a random transformation. To obtain further enhancement of this parameter a new crypto-scheme based on the advanced DDOs is proposed. The FPGA implementation of the proposed crypto-scheme achieves higher throughput value and minimizes the allocated resources than the conventional designs. Design of the DDO boxes of different orders is considered and their ASIC implementation is estimated.     

在协议集成测试系统上开展路由协议测试

在分析路由协议的特性及其测试需求的基础上，提出利用窗口黑盒来描述被测协议，利用多通道测试方法扩展对被测实现的控制和观察，通过扩充参考实现增强系统的测试能力。将这些理论，技术应用于系统中，对路由协议开展了有效的测试活动，为国产高性能路由器的开发提供了有力的支持，也进一步增强了PITS系统的功能和适用性。     

CDROM在嵌入式系统中的应用

本文介绍了嵌入式系统中利用CDROM作为大容量只读数据存储设备的设计,并通过汽车导航系统中的具体应用介绍了其软硬件电路的实现方法。     

Parallel path consistency

Filtering algorithms are well accepted as a means of speeding up the solution of the consistent labeling problem (CLP). Despite the fact that path consistency does a better job of filtering than arc consistency, AC is still the preferred technique because it has a much lower time complexity. We are implementing parallel path consistency algorithms on multiprocessors and comparing their performance to the best sequential and parallel arc consistency algorithms.^(1,2) (See also work by Kerethoet al. ⁽³⁾ and Kasif⁽⁴⁾) Preliminary work has shown linear performance increases for parallelized path consistency and also shown that in many cases performance is significantly better than the theoretical worst case. These two results lead us to believe that parallel path consistency may be a superior filtering technique. Finally, we have implemented path consistency as an outer product computation and have obtained good results (e.g., linear speedup on a 64K-node Connection Machine 2).     

用于实时数据传输的滑动帧方法及其实现

根据某雷达系统对测量信号的快速传输要求,提出采用滑动帧的处理方法并在FPGA中实现,克服了传统帧处理难以满足快速传输要求的不足。阐述了滑动帧结构的构造思想,详述了滑动帧结构的特点及具体功能模块的实现。根据实际应用需求构造了滑动帧结构处理器,试验和应用结果表明设计可行有效,能充分满足实时数据传输的要求。     

天津独流减河工程监控系统现地通信单元设计

提出一种配电网电容电流测量的新方法，在零序电压互感器的开口三角侧串联一个可调电感，通过注入一个变频恒流信号寻找配电网的谐振频率，改变可调电感的数值后寻找另一谐振频率，联立2个谐振方程求解电容电流，该方法消除了电压互感器漏抗对测量的影响。开发了配电网电容电流测量仪，经模拟试验和现场测试表明，该方法具有安全、快捷、准确等特点，适用于中性点不接地或经随调式消弧线圈接地配电网。     

基于FPGA乘法器架构的RNS与有符号二进制量转换

RNS(余数数制系统)是一种整数运算系统,在粒度精确性,能源损耗和响应速度上有很大的优势.从RNS到二进制数的输入输出转换是基于余数算法的专用架构实现的关键.本文提出了一个基于N类模的RNS与有符号二进制量的通用转换算法在FPGAs的乘法器上的实现过程.该算法能更有效地进行有符号数与RNS的转换.基于该算法类型乘法器在同类型乘法器中显示出了速度优势.文章中该架构被映射到Altera的10K系列的FPGA上.     

Viterbi译码器的硬件实现

介绍了一种Vkerbi译码器的硬件实现方法。设计的基于硬判决的Viterbi译码器具有约束长度长（9)、译码深度深（64)的特点。为了兼顾硬件资源与电路性能两个方面，在设计中使用了4个ACS单元，并根据Xilinx Virtex系列FPGA的结构特点．利用FPGA内部的BlockRAM保存汉明距离和幸存路径，提高了译码速度。     

基于非锐化掩模的实时自适应图像增强算法

针对传统的非锐化掩模算法的局限性,依据图像中各像素点及以其为中心的若干相邻像素点的均方差值,提出了自适应图像增强算法的原理,并分析其硬件实现方法,然后给出了该算法与其它算法应用于图像增强的对比结果,最后在FPGA（field programmable gate array）实验板上进行验证.实验结果表明,此算法有效的增强图像的细节区域,防止图像边缘区域出现过冲现象,抑制图像平坦区域的噪声放大.因此,该算法取得了良好的视觉效果,硬件实现简单,适合于实时条件下图像的增强.