使用FPGA与SDRAM实现液晶显示控制模块的浅析

针对液晶显示控制板上存储器(SRAM)存储量小和频率低的情况,提出了基于DDR sdram作为显示存储器的LCD显示控制器的设计。使用了灵活性与可靠性高的现场可编程门阵列(FPGA)来实现各模块的逻辑功能,分析了实现LCD显示屏控制模块的方案。     

Combined hardware–software multi-parallel prefiltering on the Convey HC-1 for fast homology detection

Protein databases used in research are huge and still grow at a fast pace. Many comparisons need to be done when searching similar (homologous) sequences for a given query sequence in these databases. Comparing a query sequence against all sequences of a huge database using the well-known Smith–Waterman algorithm is very time-consuming. Hidden Markov Models pose an opportunity for reducing the number of entries of a database and also enable to find distantly homologous sequences. Fewer entries are achieved by clustering similar sequences in a Hidden Markov Model. Such an approach is used by the bioinformatics tool HHblits. To further reduce the runtime, HHblits uses two-level prefiltering to reduce the number of time-consuming Viterbi comparisons. Still, prefiltering is very time-consuming. Highly parallel architectures and huge bandwidth are required for processing and transferring the massive amounts of data. In this article, we present an approach exploiting the reconfigurable, hybrid computer architecture Convey HC-1 for migrating the most time-consuming part. The Convey HC-1 with four FPGAs and high memory bandwidth of up to 76.8 GB/s serves as the platform of choice. Other bioinformatics applications have already been successfully supported by the HC-1. Limited by FPGA size only, we present a design that calculates four first-level prefiltering scores per FPGA concurrently, i.e. 16 calculations in total. This score calculation for the query profile against database sequences is done by a modified Smith–Waterman scheme that is internally parallelized 128 times in contrast to the original Streaming ‘Single Instruction Multiple Data (SIMD)’ Extensions (SSE)-supported implementation where only 16-fold parallelism can be exploited and where memory bandwidth poses the limiting factor. Preloading the query profile, we are able to transform the memory-bound implementation to a compute- and resource-bound FPGA design. We tightly integrated the FPGA-based coprocessor into the hybrid computing system by employing task-parallelism for the two-level prefiltering. Despite much lower clock rates, the FPGAs outperform SSE-based execution for the calculation of the prefiltering scores by a factor of 7.9.     

A scalable architecture for geometric correction of multi-projector display systems

Multi-projector displays allow the realization of large and immersive projection environments by allowing the tiling of projections from multiple projectors. Such tiled displays require real time geometrical warping of the content that is being projected from each projector. This geometrical warping is a computationally intensive operation and is typically applied using high-end graphics processing units (GPUs) that are able to process a defined number of projector channels. Furthermore, this limits the applicability of such multi-projector display systems only to the content that is being generated using desktop based systems. In this paper we propose a platform independent FPGA based scalable hardware architecture for geometric correction of projected content that allows addition of each projector channel at a fractional increase in logic area. The proposed scheme provides real time correction of HD quality video streams and thus enables the use of this technology for embedded and standalone devices.     

DVB-T调制器外码编码器的FPGA设计

设计并实现了一种DVB—T调制器的外码编码器，着重介绍了码流自适应接口、能量扩散、RS编码器及卷积交织器的设计方法，该设计方案最终在Altera的FPGA上进行验证。     

CDROM在嵌入式系统中的应用

本文介绍了嵌入式系统中利用CDROM作为大容量只读数据存储设备的设计,并通过汽车导航系统中的具体应用介绍了其软硬件电路的实现方法。     

用于实时数据传输的滑动帧方法及其实现

根据某雷达系统对测量信号的快速传输要求,提出采用滑动帧的处理方法并在FPGA中实现,克服了传统帧处理难以满足快速传输要求的不足。阐述了滑动帧结构的构造思想,详述了滑动帧结构的特点及具体功能模块的实现。根据实际应用需求构造了滑动帧结构处理器,试验和应用结果表明设计可行有效,能充分满足实时数据传输的要求。     

天津独流减河工程监控系统现地通信单元设计

提出一种配电网电容电流测量的新方法，在零序电压互感器的开口三角侧串联一个可调电感，通过注入一个变频恒流信号寻找配电网的谐振频率，改变可调电感的数值后寻找另一谐振频率，联立2个谐振方程求解电容电流，该方法消除了电压互感器漏抗对测量的影响。开发了配电网电容电流测量仪，经模拟试验和现场测试表明，该方法具有安全、快捷、准确等特点，适用于中性点不接地或经随调式消弧线圈接地配电网。     

基于FPGA乘法器架构的RNS与有符号二进制量转换

RNS(余数数制系统)是一种整数运算系统,在粒度精确性,能源损耗和响应速度上有很大的优势.从RNS到二进制数的输入输出转换是基于余数算法的专用架构实现的关键.本文提出了一个基于N类模的RNS与有符号二进制量的通用转换算法在FPGAs的乘法器上的实现过程.该算法能更有效地进行有符号数与RNS的转换.基于该算法类型乘法器在同类型乘法器中显示出了速度优势.文章中该架构被映射到Altera的10K系列的FPGA上.     

Viterbi译码器的硬件实现

介绍了一种Vkerbi译码器的硬件实现方法。设计的基于硬判决的Viterbi译码器具有约束长度长（9)、译码深度深（64)的特点。为了兼顾硬件资源与电路性能两个方面，在设计中使用了4个ACS单元，并根据Xilinx Virtex系列FPGA的结构特点．利用FPGA内部的BlockRAM保存汉明距离和幸存路径，提高了译码速度。     

基于非锐化掩模的实时自适应图像增强算法

针对传统的非锐化掩模算法的局限性,依据图像中各像素点及以其为中心的若干相邻像素点的均方差值,提出了自适应图像增强算法的原理,并分析其硬件实现方法,然后给出了该算法与其它算法应用于图像增强的对比结果,最后在FPGA（field programmable gate array）实验板上进行验证.实验结果表明,此算法有效的增强图像的细节区域,防止图像边缘区域出现过冲现象,抑制图像平坦区域的噪声放大.因此,该算法取得了良好的视觉效果,硬件实现简单,适合于实时条件下图像的增强.