结合公钥加密和关键字可搜索加密的加密方案

带关键字搜索的公钥加密(PEKS)是一种有用的加密原语，它允许用户将在加密数据上搜索的功能委托给不可信的第三方服务器，而不影响原始数据的安全性和隐私性。但是，由于缺乏对于数据的加密以及解密能力，PEKS方案不能单独进行使用，必须与标准的公钥加密方案(PKE)相结合。因此，Baek等人在2006年引入了一种新的加密原语，称为结合PKE和PEKS的加密方案(PKE+PEKS)，它同时提供了PKE和PEKS的功能。目前，已有文献提出了几种PKE+PEKS方案。然而，他们都没有考虑关键字猜测攻击的问题。本文提出一个新的高效且能够抵抗关键字猜测攻击的PKE+PEKS方案，与已有方案相比，该方案在性能上有很大的提升，并且在生成关键字和数据密文时，不需要使用双线性对，极大地降低了计算和存储成本。安全性分析表明，本文中所提出的方案能够满足密文隐私安全性、陷门不可区分性和抗关键字猜测攻击的安全性。效率分析表明，本分提出的方案更加高效。     

加快能源工业用钢开发支撑国家能源战略实施——武钢发展战略的思考

能源给人类带来光明,能源给社会进步提供了动力,尤其是进入21世纪以来,能源的可持续发展己成为直接影响世界经济社会可持续发展的决定性因素之一。中国政府高瞻远瞩地提出到2020年要实现国民经济翻两番和建设节约型社会的目标,描绘了支撑这一发展目标的十分宏伟的能源发展战略,使人振奋,也对我国钢铁产业的发展提出了更高的要求,作为长期以来与我国     

基于射频技术的无刷同步电机励磁电流的检测

无刷同步电机的励磁系统对励磁电流的测量是制约该励磁方式发展的一大障碍。设计了一个射频系统可以用来解决同步电机的励磁电流的测量问题。该系统可以方便地检测到同步电机励磁机的整流二极管的工作状态并且可以动态地显示励磁电流，极大地方便了运行人员做出判断，而且结构简单、方便实用。     

变频器调速装置节能浅析

1概述 近十多年来,随着电力电子技术、微电子技术及现代控制理论的发展,变频调速技术已经广泛地用于交流电动机的速度控制,其最主要的特点是具有高效率的驱动性能及良好的控制特性.它是一种高新技术电力节能装置,它通过改变（降低）电源工作频率,来降低动力设备（电机）的转速,减少设备的输出功率,达到输出功率与工作负荷的最佳匹配,实现节能目的,有效地提高了经济效益和产品质量.几乎可以说,有电动机的地方就有变频器,在一切需要进行速度控制的场合,变频器以其操作方便、体积小、控制性能高而获得广泛应用.     

High-performance and power-efficient CMOS comparators

Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques.     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

天然气水合物和天然气脱水新工艺探讨

探讨了天然气水合物的发展过程、形成条件以及对天然气输送管道的腐蚀堵塞作用,对我国天然气脱水创新技术———膜法脱水、汽提脱水的原理与工艺过程进行了全面论述。考察了气体处理量及操作压力等对我国1.2×105m3/d天然气膜法脱水的工业试验装置的脱水过程的影响。     

Fenton试剂降低采油污水CODCr的研究与应用

针对辽河油区超稠油采油污水的特点，采用Fenton试剂催化氧化，对采油污水处理进行研究。实验研究及现场应用结果表明，此方法对污水的CODCr具有良好的去除效果。处理后污水经过简单生化，进一步降解污染物，能够实现稳定迭标排放，且具有能耗低、运行成本低和操作简单等特点。     

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.