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This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer. A mixedsignal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time. An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current. The digital processor can automatically compensate presetting frequency variation with process and temperature, and control the operation of the auxiliary tuning loop. A 1.2 GHz integer-N synthesizer with 1 MHz reference input was implemented in a 0.18 μm process. The measured results demonstrate that the typical settling time of the synthesizer is less than 3 μs, and the phase noise is –108 dBc/Hz@1MHz. The reference spur is –52 dBc. 相似文献
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This paper presents a high-speed column-parallel cyclic analog-to-digital converter(ADC) for a CMOS image sensor.A correlated double sampling(CDS) circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise(FPN) effectively.One single channel ADC with an area less than 0.02 mm~2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors. 相似文献
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本文基于sigma-delta分数频率合成器设计了多标准I/Q正交载波产生系统。通过合理的频率规划,此系统能够应用于多标准无线通讯系统。设计采用了0.13um的标准CMOS射频工艺。测试结果显示3个正交VCO的频率覆盖范围为3.1GHz至6.1GHz(65.2%),然后通过串联的除二分频器,可以使系统的频率连续覆盖0.75GHz至6GHz。整个芯片的面积是2.1mm1.8mm。在1.2V的电源电压下系统功耗为21.7mA(除去输出缓冲级)。利用频率预置技术,锁相环的锁定时间小于4us。并且在系统中加入了非易失性存储器(NVM),能够存储系统的一些数字配置信息包括锁相环的预置信息,利用NVM的非易失存储特性,使得整个系统能够避免重复的校正。 相似文献
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This paper proposes a new structure to lower the power consumption of a variable gain amplifier (VGA) and keep the linearity of the VGA unchanged. The structure is used in a high rate amplitude-shift keying (ASK) based IF-stage. It includes an automatic gain control (AGC) loop and ASK demodulator. The AGC mainly consists of six-stage VGAs. The IF-stage is realized in 0.18 μ m CMOS technology. The measurement results show that the power consumption of the whole system is very low. The system consumes 730 μ A while operating at 1.8 V. The minimum ASK signal the system could detect is 0.7 mV (peak to peak amplitude). 相似文献
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We present a monolithic ultraviolet(UV) image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists of a CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16×16 image sensor prototype chip is implemented in a 0.18μm standard CMOS logic process.The pixel and image sensor were measured. Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/(mJ/cm~2) and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications. 相似文献
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