Latchup-free ESD protection design with complementary substrate-triggered SCR devices

The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.     

Note on ‘Construction of Double Sampling s‐Control Charts for Agile Manufacturing’

He and Grigoryan (Quality and Reliability Engineering International 2002; 18 :343–355) formulated the design of a double‐sampling (DS) s control chart as an optimization problem and solved it with a genetic algorithm. They concluded that the DS s control charts can be a more economically preferable alternative in detecting small shifts than traditional s control charts. We explain that, since they only considered the average sample size when the process is in control, their conclusion is questionable. Copyright © 2006 John Wiley & Sons, Ltd.     

Optimum power-saving method for power MOSFET width of DC/DC converters

An optimum power metal-oxide-semiconductor field effect transistor (MOSFET) width technique is proposed for enhancing the efficiency characteristics of switching DC-DC converters. By implementing a one-cycle buck DC-DC converter, it is demonstrated that the dynamic power MOSFET width controlling technique has a much improved power reduction whether the load current is light or heavy. The maximum efficiency of the buck converter is ~92% with a 3% efficiency improvement for the heavy load condition. The efficiency is further improved by ~16% for the light load condition as a result of the power reduction from the large power MOSFET transistors. Also proposed is a new error-correction loop circuit to enable a better load regulation than that of previous designs. Compared with the adaptive gate driver voltage technique, the optimum power MOSFET width can achieve a significant improvement in power saving. It is also superior to the low-voltage-swing MOSFET gate drive technique for switching DC-DC converters     

Robust State Feedback Control Through Actuators With Generalized Sector Nonlinearities And Saturation

In control systems, actuators often have nonlinear characteristics that can not be neglected. For linear systems driven by actuators satisfying the generalized sector condition, a robust state feedback controller synthesis method is proposed to achieve the ultimate boundedness control. The method is based on the linear matrix inequality approach and is easy to apply. As an important special case of the generalized sector condition, the saturation characteristic of actuators is discussed separately, and non‐conservative results are obtained.     

A Hammerstein-based dynamic model for hysteresis phenomenon

The Hammerstein configuration, which includes a nonlinear static block followed by a linear dynamic block, is applied to model the rate-dependent and temperature-dependent hysteresis phenomenon. The nonlinear static block is realized by a modified Preisach model, which includes both the irreversible and reversible components of magnetization. The linear dynamic block is realized by a low-pass filter, which takes into account the rate-dependent effects of hysteresis. Temperature dependencies are incorporated into the model by fitting the model parameters as piecewise-linear functions of temperature. A procedure is described for the extraction of a single set of model parameters over the frequency, amplitude, and temperature ranges of interest. The theory is verified experimentally     

Detection of congenital müllerian duct anomalies using three-dimensional ultrasound

PURPOSE: The purpose of this study was to assess the value of 3-dimensional sonography in the diagnosis of congenital müllerian duct anomalies, which cause infertility, preterm labor, and first trimester abortion. METHODS: A prospective study was undertaken in which 40 patients with histories of repeated spontaneous abortions or infertility were first examined using conventional 2-dimensional sonography or hysterosalpingography. Three-dimensional transvaginal sonography was then performed. RESULTS: Twenty-eight women had müllerian duct abnormalities, and 12 women had normal uterine anatomy. Müllerian duct defects detected in this study were unicornuate uterus (3), bicornuate uterus (3), complete or partial septate uterus (12), arcuate uterus (9), and didelphic uterus (1). The diagnosis of müllerian duct anomalies in these patients was confirmed by laparoscopic and/or hysteroscopic examinations. Three-dimensional sonography demonstrated all congenital uterine abnormalities with a sensitivity and specificity of 100%. Separate uterus and bicornuate uterus could be correctly diagnosed using 3-dimensional sonography in 11 (92%) of 12 cases and 3 (100%) of 3 cases, respectively. These 2 abnormalities were commonly confused with each other using hysterosalpingography and conventional sonography. CONCLUSIONS: Three-dimensional sonography with image reconstruction is less expensive and less invasive than hysterosalpingography for the assessment of uterine anatomy and diagnosis of müllerian duct abnormalities. The ability to visualize both the uterine cavity and the myometrium on a 3-dimensional scan facilitates the diagnosis of uterine anomalies and enables the differentiation of septate from bicornuate uteri for preoperative surgical planning.     

Tyrosine-dependent basolateral sorting signals are distinct from tyrosine-dependent internalization signals

Converting cysteine 543 to tyrosine in the influenza virus hemagglutinin (HA) introduces both a basolateral sorting signal and an internalization signal into the HA cytoplasmic domain. Another HA mutant, HA+8, contains eight additional amino acids at the end of the cytoplasmic domain that include a powerful internalization signal. HA+8 was also sorted efficiently to the basolateral surface of Madin-Darby canine kidney cells. The simplest explanation for the observation that multiple sorting phenotypes depend upon the same small amino acid sequence is that certain tyrosine-based internalization signals might also function as basolateral sorting signals. To test this hypothesis, second-site mutations were introduced into HA C543Y or HA+8 to determine if the internalization and basolateral sorting functions can be separated. For HA C543Y, the same sequence positions were important for both basolateral sorting and internalization, but the two functions responded differently to individual amino acid replacements, indicating that they were distinct. For HA+8, the basolateral sorting signal required the same tyrosine as the internalization signal, but did not share any other characteristics. Thus, even when basolateral sorting signals that depend on tyrosine overlap or are co-linear with internalizations signals, the two sorting processes are sensitive to different characteristics of the sequence.     

A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor

A 4-MB L2 data cache was implemented for a 64-bit 1.6-GHz SPARC(r) RISC microprocessor. Static sense amplifiers were used in the SRAM arrays and for global data repeaters, resulting in robust and flexible timing operation. Elimination of the global clock grid over the SRAM array saves power, enabled by combining the clock information with array select signals. Redundancy was implemented flexibly, with shift circuits outside the main data array for area efficiency. The chip integrates 315 million transistors and uses an 8-metal-layer 90-nm CMOS process.     

Analysing inaccurate artifact usages in workflow specifications

Although many workflow models have been proposed, analyses on artifacts are seldom discussed. A workflow application with well structured and adequate resources may still fail or yield unexpected results in execution due to inaccurate artifact manipulation, for example, inconsistency between data flow and control flow, or contradictions between artifact operations. Thus, artifact analysis is very important since activities cannot be executed properly without accurate information. This paper presents a three-layer workflow model for designing a workflow and characterises the behaviour of an artifact by its state transition diagram. By abstracting common usages of artifacts, six types of inaccurate artifact usage affecting workflow execution are identified and a set of algorithms to detect these inaccurate usages in workflow specifications is presented. An example is demonstrated and then related works are compared.     

A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme

This paper describes a 32-KB two-read, one-write ported L0 cache for 4.5-GHz operation in 1.2-V 130-nm dual-V/sub TH/ CMOS technology. The local bitline uses a leakage-tolerant self reverse-bias (SRB) scheme with nMOS source-follower pullup access transistors, while preserving robust full-swing operation. Gate-source underdrive of -220 mV on the bitline read-select transistors is established without external bias voltages or gate-oxide overstress. Device-level measurements in the 130-nm technology show 72/spl times/ bitline active leakage reduction, enabling low-V/sub TH/ usage, 40% bitline keeper downsizing, and 16 bitcells/bitline. 11% faster read delay and 2/spl times/ higher dc noise robustness are achieved compared with high-performance dual-V/sub TH/ bitline scheme. Sustained performance and robustness benefits of the SRB technique against conventional dynamic bitline with scaling to 100- and 70-nm technology is also presented.