We present a new scheme for visibly-opaque but near-infrared-transmitting filters involving 7 layers based on one-dimensional ternary photonic crystals, with capabilities in reaching nearly 100% transmission efficiency in the near-infrared region. Different decorative reflection colors can be created by adding additional three layers while maintaining the near-infrared transmission performance. In addition, our proposed structural colors show great angular insensitivity up to ±60° for both transverse electric and transverse magnetic polarizations, which are highly desired in various fields. The facile strategy described here involves a simple deposition method for the fabrication, thereby having great potential in diverse applications such as image sensors, anti-counterfeit tag, and optical measurement systems.
Rheological properties of MR fluids under large step strain shear are presented in this paper. The experiments were carried out using a rheometer with parallel-plate geometry. Under the large step strain shear, MR fluids behave as nonlinear viscoelastic properties, where the stress relaxation modulus, G(t, γ), shows a decreasing trend with step strain. The experimental results indicate that G(t, γ) obeys time-strain separability. Thus, a mathematical form based on finite exponential serials is proposed to predict MR behavior. In this model, G(t, γ) is represented as the product of a linear stress relaxation, G(t), and the damping function, h(γ), i.e. G(t, γ)=G(t) h(γ). G(t) is simply represented as a three-parameter exponential serial and h(γ) has a sigmoidal form with two parameters. The parameters are identified by adopting an efficient optimization method proposed by Stango et al. The comparison between the experimental results and the model-predicted values indicates that this mathematical model can accurately predict MR behavior. 相似文献
Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques. 相似文献
A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW. 相似文献
Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory. 相似文献