聚氨酯分散剂在液体靛蓝制备中的应用

采用异佛尔酮二异氰酸酯(IPDI)、聚乙二醇200、400、600、800(PEG200、PEG400、PEG600、PEG800)、2,2-二羟甲基丙酸(DMPA)、1-苯基-1,2-乙二醇、中和剂三乙胺(TEA)、甲乙酮肟等为原料,制备了一种阴离子聚氨酯分散剂.通过FTIR、GPC、TG表征了分散剂的结构与性能.利用自制的分散剂采用研磨法制备了液体靛蓝分散液,以液体靛蓝分散液粒径、离心稳定性、储存稳定性为指标,探讨了分散剂链长、用量对分散液性能的影响.结果表明,研磨1 h后,以PEG400为软段合成的聚氨酯分散剂用量为染料质量的60％时制备的液体靛蓝粒径为277.1 nm,1000 r/min离心稳定性达到93.98％,3000 r/min离心稳定性为51.13％,常温放置7 d后粒径变化在20 nm以内,染色后织物的颜色深度(K/S)为10左右,约是粉状靛蓝染色K/S的2倍,染色织物的颜色性能并未改变,SEM显示分散体颗粒大小分布均匀,与分散剂甲基萘磺酸钠的甲醛缩合物(MF)和木质素85A相比,其分散体系稳定性差别不大.     

太赫兹脉冲焦平面成像技术的发展与应用

作为太赫兹技术中的重要组成部分,太赫兹脉冲焦平面成像一经问世就引起了行业内的广泛关注,人们引入了各种方法去提升此成像技术的测量性能,同时也尝试将此成像技术应用于不同的工业和基础研究领域。本文综述了近年来人们对太赫兹脉冲焦平面成像的技术改良和应用研究,包括提升成像系统的空间分辨率、信噪比、信息获取能力,以及将此成像技术应用于光谱识别检测、超表面器件功能验证、太赫兹特殊光束测量、太赫兹表面波观测等,希望该综述能够推动太赫兹脉冲焦平面成像的进一步技术革新和应用拓展。     

Control of reactive distillation production of high-purity isopropanol

The process characteristics and control strategy of a high-purity IPA reactive distillation column were investigated. A robust nominal operation was found by maintaining an excess of propylene feed to the column and recycling the unreacted propylene to the feed instead of the top stage. Stage temperature and propylene composition with one-to-one relationship with reboiler duty and propylene feed are selected as controlled variables for maintaining bottom purity and feed ratio in the presence of possible measurement bias respectively. High nonlinearity between selected input–output pair was reduced by using variable transformation. Dynamic simulations demonstrated that such a control scheme with nonlinear transformed variable was capable of providing much superior control performance than the one using natural variable.     

On a New Method for H2 -Based Decomposition

This note proposes a simple linear matrix inequality (LMI) system for the design of static precompensators to reduce the interactions of a multivariable system. The approach is based on minimizing the H₂ norm of a modified system and the LMIs are derived from the well known technique of pseudodiagonalisation. The approach is applied to two complex real-life benchmark problems with high levels of interaction. It is shown that its performance is significantly better than previously proposed LMI optimization techniques for designing static precompensators     

打造自己最新版本的集成安装软件

主要阐述了软件与补丁程序的整合方法.     

保留Word文档的修改痕迹

介绍几种保留Word文档的修改痕迹的方法.     

Effects of Rare Earths on Toughness of 31Mn2SiRE Wear-Resistance Cast Steel

The toughness of 31Mn2SiRE wear-resistance cast steel were increased by means of RE compound modification and high temperature austenitizing. The results show that the microstructures can be refined, needle and network ferrite are eliminated, the dislocation density and the quantity of dislocated martensite are increased remarkably, and the shape and distribution of inclusions are improved by the addition of RE. Therefore, the mechanical properties of the modified steel can be greatly increased, especially the toughness (αK) by 44%, yield strength (σs) by 10%, and elongation (δ5) by 42%.     

High-performance and power-efficient CMOS comparators

Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques.