A floating-body charge monitoring technique for partially depleted SOI technology

This paper presents a floating-body charge monitoring technique, which does not require the use of body contacts on the device being monitored. A charge monitor is placed along side with the circuit that is susceptible to the floating-body effects in partially depleted (PD) SOI CMOS circuits. It mimics the circuit topology and operating history of a concerned circuit, specifically the worst-case body voltage of the critical device(s) under consideration. The monitoring is achieved by intentionally triggering a parasitic bipolar current pulse and setting the a state recording latch, which subsequently activates the speed recovering circuitry that compensates the loss of performance at critical circuit nets due to the presence of parasitic bipolar current. Implementation examples are given and described. This technique restores performance and improves timing robustness of the MUX-type and SRAM bit line circuits by minimizing the delay degradation or variation from parasitic bipolar currents.     

A self-aligned nitrogen implantation process (SNIP) to minimizefield oxide thinning effect in submicrometer LOCOS

A self-aligned nitrogen implantation process (SNIP) utilizing low-energy and high-dose molecular nitrogen ions has been developed to minimize the field oxide thinning effect in submicrometer local oxidation of silicon (LOCOS) isolation. Molecular nitrogen ions with a dosage of 2.5×10¹⁶ cm^-2 were implanted at 20 keV into large isolation regions to selectively form a thin nitridelike layer which can effectively retard the thermal oxidation of silicon. Self-aligned spacers were developed to shield small-isolation regions from the nitrogen implantation. The oxidation rate in small-isolation regions was therefore not affected. The final field oxide thickness became more uniform for various isolation dimensions across the wafer. The device characteristics of the n- and p-MOSFET with the SNIP were similar to those of devices with the conventional LOCOS process. An increase in the magnitude of field threshold voltages at submicrometer isolation regions was measured for both n- and p-channel parasitic field-effect transistors with the SNIP. A minimal reduction in field oxide thickness of less than 10% and an acceptable field threshold voltage magnitude of higher than 7.5 V were achieved for an isolation width as narrow as 0.5 μm     

SRAM bitline circuits on PD SOI: advantages and concerns

This paper presents a study of sub-0.25-μm CMOS SRAM bitline circuitry on partially depleted (PD) silicon-on-insulator (SOI) technology. SOI implementations outperform conventional bulk ones due to significant reduction of collective device junction capacitance on the bitlines. Floating body effects are investigated for both read and write cycles. Array content dependent behaviors are identified for the first time and analyzed with worst-case temporal and spatial pattern combinations     

Oxygen implantation to suppress parasitic bipolar action in CMOS

Oxygen implantation and subsequent epitaxial silicon deposition have been developed to improve CMOS latchup prevention through reducing the current gains of parasitic bipolar transistors. The buried oxygen implanted layer is well confined, and defects do not extend into the epitaxial silicon layer. The device characteristics of the n- and p-MOSFETs fabricated on a wafer with the oxygen implantation are therefore not affected by the buried implanted layer. The oxygen implanted layer can reduce the minority-carrier lifetime and hence decrease the current gain of the lateral parasitic bipolar transistor. In addition, it introduces a potential barrier which decreases the current collected at the frontside contact of the vertical parasitic bipolar transistor. The common base current gain is reduced by 50% and 80% for the lateral and the vertical parasitic bipolar transistors, respectively. As a consequence, the CMOS latchup immunity is significantly improved     

Effect of emitter contact materials on high-performance verticalp-n-p transistors

Ion-implant doped polysilicon, in situ doped polysilicon, and in situ doped ultrahigh vacuum chemical vapor deposition (UHV/CVD) low-temperature epitaxial silicon emitter contacts were used to fabricate shallow junction vertical p-n-p transistors. The effect of these materials on emitter junction depth and on device characteristics is reported. A DC current gain as high as 45 was measured on polysilicon emitter devices. Regardless of emitter contact material, all devices showed sufficiently high breakdown voltages for circuit applications. However, only for ion-implant doped polysilicon emitter devices was the narrow-emitter effect observed through the emitter-collector punchthrough voltage, emitter resistance, and current gain measurements