Analysis of stepwise charging limits and its implementation for efficiency improvement in switched capacitor DC–DC converters

In this work we analysed the stepwise charging technique to find the limits from which it is beneficial in terms of load capacitance and charge–discharge frequency. We included in the analysis practical limitations such as the consumption of auxiliary logic needed to implement the technique and the minimum size of auxiliary switches imposed by the technology. We proposed an ultra-low-power logic block to push these limits and to obtain benefits from this technique in small capacitances. Finally, we proposed to use a stepwise driver in the driving of the gate capacitance of power switches in switched-capacitor (SC) DC–DC converters. We designed and manufactured, in a 130 nm process, a SC DC–DC converter and measured a 29% energy reduction in the gate-drive losses of the converter. This accounts for an improvement of 4% (from 69 to 73%) in the overall converter efficiency.

     

Signal probability for reliability evaluation of logic circuits

As integrated circuits scale down into nanometer dimensions, a great reduction on the reliability of combinational blocks is expected. This way, the susceptibility of circuits to intermittent and transient faults is becoming a key parameter in the evaluation of logic circuits, and fast and accurate ways of reliability analysis must be developed. This paper presents a reliability analysis methodology based on signal probability, which is of straightforward application and can be easily integrated in the design flow. The proposed methodology computes circuit’s signal reliability as a function of its logical masking capabilities, concerning multiple simultaneous faults occurrence.     

Design of Down-Sampling Processors for Radio Communications

This paper deals with design and implementation of digital filter processors to be used as down-samplers in wireless transceivers. We consider a homodyne direct conversion and propose an improved method to specify each stage of the cascade structure. The proposed scheme results in a globally compact implementation. The method is detailed for DECT standard and illustrated by a fixed point FPGA based implementation.     

Analog to digital conversion: technical aspects

An ideal radio communication receiver places the analog to digital conversion just after the antenna. It is an objective in a “software radio” perspective. The available silicon technologies do not provide the performance required by this application. We are able to evaluate the present limits and the gap between these limits and the ideal solution proposed. In this paper, we describe the present possibilities in terms of receiver architectures and we deduce theAdc specifications. Then we analyse differentAdc architectures adapted to this application. The choice is mainly between pipeline and sigma- deltaAdc. We compare them in terms of power consumption and we introduce a factor of merit. The future technologies will have an impact onAdc performance. Superconductor technology applied toAdc may be a solution and it is analysed at the end of this paper.     

FIFA: A fault-injection–fault-analysis-based tool for reliability assessment at RTL level

This paper presents an efficient platform for fault robustness estimation of digital circuits. The proposed platform, named FIFA, was designed as a hardware IP to accelerate the Fault Injection and Fault masking Analysis approach. It supports several fault models as well as single and multiple faults. Synthesis results have shown that the proposed platform can exceed those existent in the literature in terms of area efficiency and performance. In addition, the FIFA platform allows the designer to control complexity and completeness of the analysis process.     

On design and implementation of a decimation filter for multistandard wireless transceivers

In this work, we deal with the design and implementation of a decimation filter to be used in wideband radio-frequency receiver. The paper outlines architecture considerations for multistandard wireless transceivers. Also, it describes the design steps and the tradeoffs concerning the hardware implementation. GSM and DECT standards specifications are met by the proposed filtering cascade structure. The filter processes six-bit data stream input from a fourth-order sigma-delta modulator and has been prototyped in a field-programmable gate array device.     

A survey of in-spin transfer torque MRAM computing

Science China Information Sciences -     

Flexible and reconfigurable receiver architecture for WCDMA systems with low spreading factors

A flexible and reconfigurable receiver architecture for the WCDMA high data rate connections is presented. The proposed architecture consists of a single computational unit featuring the demodulation of one channel path and the suppression of one term of the inter-path interference with minimal configuration logic and routing. This unit is used in a serial fashion to perform the total channel demodulation and IPI suppression. It is controlled by the supervisor, an intelligent architectural element, in order to optimise system performance over a computational power constraint.     

Reliability aware design of low power continuous-time sigma–delta modulator

Circuit reliability has become a major bottleneck due to ageing degradation. In this paper, reliability-aware methodology and ageing analysis of low power sigma–delta (ΣΔ) modulator are presented. HCI and NBTI are considered as the dominating ageing effects. A second order continuous-time (CT) ΣΔ modulator is implemented for medical application. Ageing estimation is performed at both behavioral and transistor level. Results at behavioral level and transistor level show that the feedback loop in CT ΣΔ modulator is more sensitive and less reliable than the analog loop filter. Comparing with HCI, NBTI is the dominating ageing effect in the designed CT ΣΔ modulator.