Formalized three-layer system-level model and reuse methodology forembedded data-dominated applications

In embedded data-dominated applications, a global system-level data transfer and storage exploration phase is crucial in obtaining a cost- and performance-efficient solution. We have developed a novel formalism to describe reusable blocks such that the essential part of the design exploration freedom is retained. This formalism is the basis for a system-level reuse methodology which allows reusing large parts of the design as heavily optimized structural VHDL or assembly code and describes the costly data access-related constructs at higher levels in the code hierarchy. Compared to a reuse approach based on fixed blocks, considerable power and area savings can be obtained, as demonstrated on real-life video and modem applications     

A Safari Through the MPSoC Run-Time Management Jungle

The multiprocessor SoC (MPSoC) revolution is fueled by the need to execute multiple advanced multimedia applications on a single embedded computing platform. At design-time, the applications that will run in parallel and their respective user requirements are unknown. Hence, a run-time manager (RTM) is needed to match all application needs with the available platform resources and services. Creating such a run-time manager requires two decisions. First, one needs to decide what functionality to implement. Second, one has to decide how to implement this functionality in order to meet boundary conditions like e.g. real-time performance. This paper is the first to detail a generic view on MPSoC run-time management functionality and its design space trade-offs. We substantiate the run-time components and the implementation trade-offs with academic state-of-the-art solutions and a brief overview of some industrial multiprocessor run-time management examples. We show a clear trend towards more hardware acceleration, a limited distribution of management functionality over the platform and increasing support for adaptive multimedia applications. In addition, we briefly detail upcoming run-time management research issues.     

No pain, no gain: The conditions under which upward comparisons lead to better performance.

In 3 studies, the authors explored the relation between threatening upward social comparisons and performance. In an initial study, participants were exposed to comparison targets who either threatened or boosted self-evaluations and then completed a performance task. Participants exposed to the threatening target performed better than those in a control group, whereas those exposed to the nonthreatening target performed worse. In Study 2, self-affirmation prior to comparison with threatening targets eliminated performance improvements. In Study 3, performance improvements were found only when the performance domain was different from the domain of success of the comparison target. These boundary conditions suggest that increases in performance following social comparison arise from individuals' motivations to maintain and repair self-evaluations. Implications for the study of the behavioral consequences of social comparison are discussed. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

On the comparison of HOL and Boyer-Moore for formal hardware verification

Faced with the challenge of designing correct circuits, the research community has been applying alternative verification methodologies istead of only traditional methods like ad hoc simulation. The best choice among alternatives like tautology checking, symbolic simulation, and theorem proving depends very theorem proving is best applicable, one is faced with the problem of choosing a formalism. This article compares the proof assistant HOL and the theorem-prover Boyer-Moore based on a practical experience with both systems in order to verify a combinatorial and parameterized hardware module from the CATHEDRAL II Silicon Compiler library. Although the comparison is based on a specific application, the general features, advantages, and drawbacks of both systems are discussed, with consideration given to the verification of other kinds of circuits.     

Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management

MATISSE is a design environment intended for developing systems characterized by a tight interaction between control and data-flow behavior, intensive data storage and transfer, and stringent real-time requirements. Matisse bridges the gap from a system specification, using a concurrent object-oriented language, to an optimized embedded single-chip hardware/software implementation. Matisse supports stepwise exploration and refinement of dynamic memory management, memory architecture exploration, and gradual incorporation of timing constraints before going to traditional tools for hardware synthesis, software compilation, and inter-processor communication synthesis. With this approach, specifications of embedded systems can be written in a high-level programming language using data abstraction. Application of MATISSE on telecom protocol processing systems in the ATM area shows significant improvements in area usage and power consumption.     

Exploiting Varying Resource Requirements in Wavelet-based Applications in Dynamic Execution Environments

In the context of future dynamic applications, systems will exhibit unpredictably varying platform resource requirements. To deal with this, they will not only need to be programmable in terms of instruction set processors, but also at least partial reconfigurability will be required. In this context, it is important for applications to optimally exploit the memory hierarchy under varying memory availability. This article presents a mapping strategy for wavelet-based applications: depending on the encountered conditions, it switches to different memory optimized instantations or localizations, permitting up to 51% energy gains in memory accesses. Systematic and parameterized mapping guidelines indicate which localization should be selected when, for varying algorithmic wavelet parameters. The results have been formalized and generalized to be applicable to more general wavelet-based applications.