Systematic characterization of Cl2 reactive ion etchingfor improved ohmics in AlGaN/GaN HEMTs

Pre-metal-deposition reactive ion etching (RIE) was performed on an Al_0.3Ga_0.7N/AlN/GaN heterostructure in order to improve the metal-to-semiconductor contact resistance. An optimum AlGaN thickness for minimizing contact resistance was determined. An initial decrease in contact resistance with etching time was explained in terms of removal of an oxide surface layer and/or by an increase in tunnelling current with the decrease of the AlGaN thickness. The presence of a dissimilar surface layer was confirmed by an initial nonuniform etch depth rate. An increase in contact resistance for deeper etches was experienced. The increase was related to depletion of the two-dimensional (2-D) electron gas (2-DEG) under the ohmics. Etch depths were measured by atomic force microscopy (AFM). The contact resistance decreased from about 0.45 Ωmm for unetched ohmics to a minimum of 0.27 Ωmm for 70 Å etched ohmics. The initial thickness of the AlGaN layer was 250 Å. The decrease in contact resistance, without excessive complications on device processing, supports RIE etching as a viable solution to improve ohmic contact resistance in AlGaN/GaN HEMTs     

Accelerating scientific computations with mixed precision algorithms

On modern architectures, the performance of 32-bit operations is often at least twice as fast as the performance of 64-bit operations. By using a combination of 32-bit and 64-bit floating point arithmetic, the performance of many dense and sparse linear algebra algorithms can be significantly enhanced while maintaining the 64-bit accuracy of the resulting solution. The approach presented here can apply not only to conventional processors but also to other technologies such as Field Programmable Gate Arrays (FPGA), Graphical Processing Units (GPU), and the STI Cell BE processor. Results on modern processor architectures and the STI Cell BE are presented.

Program summary

Program title: ITER-REFCatalogue identifier: AECO_v1_0Program summary URL:http://cpc.cs.qub.ac.uk/summaries/AECO_v1_0.htmlProgram obtainable from: CPC Program Library, Queen's University, Belfast, N. IrelandLicensing provisions: Standard CPC licence, http://cpc.cs.qub.ac.uk/licence/licence.htmlNo. of lines in distributed program, including test data, etc.: 7211No. of bytes in distributed program, including test data, etc.: 41 862Distribution format: tar.gzProgramming language: FORTRAN 77Computer: desktop, serverOperating system: Unix/LinuxRAM: 512 MbytesClassification: 4.8External routines: BLAS (optional)Nature of problem: On modern architectures, the performance of 32-bit operations is often at least twice as fast as the performance of 64-bit operations. By using a combination of 32-bit and 64-bit floating point arithmetic, the performance of many dense and sparse linear algebra algorithms can be significantly enhanced while maintaining the 64-bit accuracy of the resulting solution.Solution method: Mixed precision algorithms stem from the observation that, in many cases, a single precision solution of a problem can be refined to the point where double precision accuracy is achieved. A common approach to the solution of linear systems, either dense or sparse, is to perform the LU factorization of the coefficient matrix using Gaussian elimination. First, the coefficient matrix A is factored into the product of a lower triangular matrix L and an upper triangular matrix U. Partial row pivoting is in general used to improve numerical stability resulting in a factorization PA=LU, where P is a permutation matrix. The solution for the system is achieved by first solving Ly=Pb (forward substitution) and then solving Ux=y (backward substitution). Due to round-off errors, the computed solution, x, carries a numerical error magnified by the condition number of the coefficient matrix A. In order to improve the computed solution, an iterative process can be applied, which produces a correction to the computed solution at each iteration, which then yields the method that is commonly known as the iterative refinement algorithm. Provided that the system is not too ill-conditioned, the algorithm produces a solution correct to the working precision.Running time: seconds/minutes     

High-power polarization-engineered GaN/AlGaN/GaN HEMTs without surface passivation

In this paper, a high-power GaN/AlGaN/GaN high electron mobility transistor (HEMT) has been demonstrated. A thick cap layer has been used to screen surface states and reduce dispersion. A deep gate recess was used to achieve the desired transconductance. A thin SiO/sub 2/ layer was deposited on the drain side of the gate recess in order to reduce gate leakage current and improve breakdown voltage. No surface passivation layer was used. A breakdown voltage of 90 V was achieved. A record output power density of 12 W/mm with an associated power-added efficiency (PAE) of 40.5% was measured at 10 GHz. These results demonstrate the potential of the technique as a controllable and repeatable solution to decrease dispersion and produce power from GaN-based HEMTs without surface passivation.     

Power and linearity characteristics of field-plated recessed-gate AlGaN-GaN HEMTs

Record power density and high-efficiency operation with AlGaN-GaN high-electron mobility transistor (HEMT) devices have been achieved by adopting a field-plated gate-recessed structure. Devices grown on SiC substrate yielded very high power density (18.8 W/mm with 43% power-added efficiency (PAE) as well as high efficiency (74% with 6 W/mm) under single-tone continuous-wave testing at 4 GHz. Devices also showed excellent linearity characteristics when measured under two-tone continuous-wave signals at 4 GHz. When biased in deep-class AB (33 mA/mm, 3% I/sub max/) device maintained a carrier to third-order intermodulation ratio of 30 dBc up to a power level of 2.4 W/mm with 53% PAE; increasing bias current to 66 mA/mm (6% I/sub max/) allowed high linear operation (45 dBc) up to a power level of 1.4 W/mm with 38% PAE.     

2.1 A/mm current density AlGaN/GaN HEMT

The electrical performance of high current density AlGaN/GaN HEMTs is reported. 2 /spl times/ 75 /spl mu/m /spl times/ 0.7 /spl mu/m devices grown on sapphire substrates showed current densities up to 2.1 A/mm under 200 ns pulse condition. RF power measurements at 8 GHz and V/sub DS/=15 V exhibited a saturated output power of 3.66 W/mm with a 47.8% peak PAE.     

Effect of p-doped overlayer thickness on RF-dispersion in GaNjunction FETs

Successive reactive ion etchings (RIE) were performed on the access regions of p⁺-n GaN JFETs. A decrease in the n-layer sheet resistance, with a consequent increase in I_DSS was detected after complete removal of the p-layer, due to a reduction in the n-layer depletion region. An increase in RF-dispersion was experienced, as a result of the progressive reduction of screening from surface-states originally provided by the overlying p-cap layer. No dispersion was detected before cap removal. A continuous increase in f _t and f_max was detected even before complete removal of the p-layer, due to virtual gate length reduction. It is expected that an optimized p-doped overlayer will provide current slump suppression without degradation in cutoff frequency or breakdown     

Parasitic effects and long term stability of InP-based HEMTs

A study of InP based HEMTs implemented with different process options will be reported. It will be demonstrated that devices with an InP etch stopper layer or with a narrow lateral gate recess region do not present any kink effect, neither any transconductance frequency dispersion, g_m(f) and a stable behavior with respect to hot electron aging is observed. The opposite occurs in devices without the InP etch stopper layer and a wide lateral gate recess region. The data presented confirm the effectiveness of an InP passivating layer in improving the reliability of advanced InP-HEMTs, and point out at the free InAlAs surface as responsible for the observed instabilities (kink effects, g_m(f) dispersion).     

2LEV-D2P4: a package of high-performance preconditioners for scientific and engineering applications

We present a package of parallel preconditioners which implements one-level and two-level Domain Decomposition algorithms on the top of the PSBLAS library for sparse matrix computations. The package, named 2LEV-D2P4 (Two-LEVel Domain Decomposition Parallel Preconditioners Package based on PSBLAS), currently includes various versions of additive Schwarz preconditioners that are combined with a coarse-level correction to obtain two-level preconditioners. A pure algebraic formulation of the preconditioners is considered. 2LEV-D2P4 has been written in Fortran~95, exploiting features such as abstract data type creation, functional overloading and dynamic memory management, while providing a smooth path towards the integration in legacy application codes. The package, used with Krylov solvers implemented in PSBLAS, has been tested on large-scale linear systems arising from model problems and real applications, showing its effectiveness.     

Solving Systems of Linear Equations on the CELL Processor Using Cholesky Factorization

The Sony/Toshiba/IBM (STI) CELL processor introduces pioneering solutions in processor architecture. At the same time it presents new challenges for the development of numerical algorithms. One is effective exploitation of the differential between the speed of single and double precision arithmetic; the other is efficient parallelization between the short vector SIMD cores. The first challenge is addressed by utilizing the well known technique of iterative refinement for the solution of a dense symmetric positive definite system of linear equations, resulting in a mixed-precision algorithm, which delivers double precision accuracy, while performing the bulk of the work in single precision. The main contribution of this paper lies in addressing the second challenge by successful thread-level parallelization, exploiting fine-grained task granularity and a lightweight decentralized synchronization. The implementation of the computationally intensive sections gets within 90 percent of peak floating point performance, while the implementation of the memory intensive sections reaches within 90 percent of peak memory bandwidth. On a single CELL processor, the algorithm achieves over 170~Gflop/s when solving a symmetric positive definite system of linear equation in single precision and over 150~Gflop/s when delivering the result in double precision accuracy.     

Oxidation control of GaAs pHEMTs for high efficiency applications

In this letter, for the first time, an investigation of partially oxidized GaAs-on-insulator (GOI) AlGaAs/InGaAs/GaAs pseudomorphic HEMTs is reported. Fully oxidized pHEMTs demonstrated minimized substrate leakage current and high output impedance, but suffered from 30~40% charge loss. Fully oxidized devices also showed transconductance peaking that could be removed by controlled partial oxidation. Partially oxidized pHEMT devices showed improved power added efficiencies (PAEs) at a low supply voltage of 3.0 V compared to fully oxidized or unoxidized devices and negligible charge loss (<10%)