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SOC用400-800MHz锁相环IP的设计 总被引:4,自引:0,他引:4
设计了一个基于锁相环结构、可应用于SOC设计的时钟产生模块.电路输出频率在400~800 MHz,使用SMIC 0.18 μm CMOS工艺进行流片.芯片核心模块工作电压为1.8 V和3.3 V.根据Hajimi关于VCO中抖动(jitter)的论述,为了降低输出抖动,采用一种全差动、满振幅结构的振荡器;同时,通过选取合适的偏置电流,实现对环路带宽的温度补偿.流片后测试结果为:输出频率范围400~800 MHz,输入频率40~200 MHz;在输出频率为800 MHz时,功耗小于23 mA,周期抖动峰峰值为62.5 ps,均方根(rms)值为13.1 ps,芯片面积0.6 mm2. 相似文献
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设计了一种时钟产生电路,该电路采用基于低功耗锁相环(PLL)的方法,用于产生13.56MHz ASK100%、10%调制射频卡所需要的时钟。针对射频识别(RFID)系统,锁相环采取了特殊的设计。本电路作为模块可应用于符合ISO/IEC15693、ISO/IEC18000-3标准的非接触IC卡中。通过Cadence spectre软件,使用0.35μm互补金属氧化物半导体(CMOS)工艺模型进行验证。仿真结果显示:电路采用3.3V电源供电时,100%调制载波幅度为0%时,总工作电流仅为17μA。 相似文献
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Modeling and analysis of far field power extraction circuits for passive UHF RF identification (RFID) applications are presented. A mathematical model is derived to predict the complex nonlinear performance of UHF voltage multiplier using Schottky diodes. To reduce the complexity of the proposed model, a simple linear approximation for Schottky diode is introduced. Measurement results show considerable agreement with the values calculated by the proposed model. With the derived model, optimization on stage number for voltage multiplier to achieve maximum power conversion efficiency is discussed. Furthermore, according to the Bode-Fano criterion and the proposed model, a limitation on maximum power up range for passive UHF RFID power extraction circuits is also studied. 相似文献
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