Grain-Size Dependence of Fracture Energy in Ceramics

A simple model incorporating thermal elastic anisotropy stresses is used to calculate the microcrack zone size around cracks in Al₂O₃. It is found that the ratio of microcrack zone size to grain size is almost constant for notched beam tests, but increases with grain size for double cantilever beam data. It is suggested that notched-beam ratios of fracture toughness are related to crack initiation, whereas double cantilever beam values are related to propagation and reflect R-curve behavior of the material.     

Kroll process beryllium

High-purity beryllium metal was prepared on a laboratory scale by Kroll process procedures in which sodium was used as a reductant. Crude beryllium chloride, purchased from commercial sources, was purified by vacuum sublimation and fused-salt scrubbing. Purified beryllium chloride was vaporized and reacted at a controlled rate with molten sodium at temperatures ranging from 650° to 750°C to form beryllium sponge. Excess metal reductant and byproduct salt were removed from the sponge metal by vacuum distillation. Beryllium sponge metal was wet ball milled to ?200 or ?400 mesh powders. Beryllium powder metal, subsequently consolidated by isostatic pressing, was hot extruded and machined into tensile specimens for evaluation of mechanical properties. Evaluation indicates that the beryllium described in this study is of higher purity than comparable commercial grades of metal; also it is more ductile but has somewhat lower strength. The overall process appears to have an excellent potential from an economic standpoint.     

Influence of the epitaxial growth and device processing on the overlay accuracy during processing of the d-DotFET

To maintain the development of MOSFET devices in the last three decades the lateral layout of this important device was scaled down into the sub-50 nm range. The challenge to maintain device performance was met by applying to scaling rules, which ensure a proper physical behaviour in the active area of the device. But nowadays new device architectures as Ultra Thin Body and Multi Gate devices have to be discussed. Furthermore new materials were introduced as high-κ gate dielectrics and metal gates. In recent years strained silicon has drawn increasing attention to enlarge carrier mobility in the MOSFET channel. In the d-DotFET approach locally strained silicon is formed by means of template-assisted self assembly of Ge-dots and silicon overgrowth. The silicon capping layer is strained on top of the dot and in its near vicinity, only. The accurate positioning of the dots on pre-patterned substrates enables the utilization of these substrates for further device processing. The crucial issue is to integrate the active area on top of the dot, which requires an overlay of ± 10 nm, which has to be assured over the whole process. In this paper we investigate the intrinsic overlay of a Vistec EBPG 5000^plus e-beam system using etched holes in silicon as markers. It was found, that the required overlay accuracy can be obtained, when the definition of the marker sites is adapted to the following process, already. The overlay is not affected by device processing, as long as the markers are affected symmetrically.     

Integration of MOSFETs with SiGe dots as stressor material

The potentials of using silicon-germanium dots as stressor material in MOSFETs are evaluated with respect to integration in today’s production processes. Work is reviewed that has lead to the fabrication of the first experimental n-channel MOSFETs on SiGe dots, referred to as DotFETs, in a low-complexity, custom-made low-temperature process where the dot is preserved during the entire device processing. The SiGe dots were grown in large regular arrays in a Stranski-Krastanow (S-K) mode and used to induce biaxial tensile strain in a silicon capping-layer. The DotFETs are processed with the main gate-segment above the strained Si layer on a single dot. To prevent intermixing of the Si/SiGe/Si structure, the processing temperature is kept below 400 °C by using excimer-laser annealing to activate the source/drain implants that are self-aligned to a metal gate. The crystallinity of the structure is preserved throughout the processing and, compared to reference devices, an average increase in drain current up to 22.5% is obtained. The experimental results are substantiated by extensive simulations and modeling of the strain levels in capped dots and the corresponding mobility enhancement achievable with DotFETs. The concept of SiGe dots overgrown with a Si layer is also considered for use as a starting structure for silicon-on-nothing (SON) technology where the dot should be removed after the formation of the gate-stack and the strain for mobility enhancement should be preserved (and possibly increased) via the other device layers.     

InP quantum dots in (1 0 0) GaP: Growth and luminescence

We describe the growth and optical emission from strained InP quantum wells and quantum dots grown on GaP substrates using gas-source molecular beam epitaxy. Self-organized quantum dot formation takes place for InP coverage greater than 1.8 monolayers on the (1 0 0) GaP surface. Atomic force and scanning-electron microscopy studies indicate that unburied dots have a lateral size of 60–100 nm and are about 20 nm high, with dot densities in the range of 2–6×10⁸ cm⁻² for InP coverage between 1.9 and 5.8 MLs. Intense photoluminescence is emitted from both the quantum wells and the quantum dots at energies of about 2.2 and 2.0 eV, respectively. Time-resolved measurements indicate rather long carrier lifetimes of about 19 ns in the quantum wells and about 3 ns in the quantum dots. The data indicate that the InP/GaP quantum wells form a type-II band system, with electrons in the X valleys of the GaP recombine with holes in the InP. Furthermore, in the InP/GaP quantum dot system, the conduction band edge in the X valley of the GaP is nearly aligned with that in the Γ valley of the InP. Rapid thermal annealing of the quantum dots results in at least a six-fold enhancement of integrated emission intensity as well as some Ga-In interdiffusion. The low interdiffusion activation energy indicates that the material near the interface between the GaP matrix and the InP dots is not free of defects.     

Investigation of the local Ge concentration in Si/SiGe nanostructures by convergent-beam electron diffraction

SiGe multi quantum well structures were investigated by convergent-beam electron diffraction (CBED) measurements. Detailed layer characterizations were performed by acquiring series of bright field CBED patterns in the form of a line scan across the nanostructures in scanning transmission electron microscopy (STEM) mode. From the higher order Laue zone (HOLZ) lines the local lattice parameters were deduced. The Ge concentration corresponding to these lattice parameters was determined by means of the elasticity theory. In this work it is shown that the lattice constants can be determined locally with an accuracy of about ±0.001 to ±0.003 Å which leads to an accuracy of the corresponding Ge concentration of about 1–2%. The characteristics of the focused electron probe and its influence on the experimental data were used for an estimation of the spatial resolution of the CBED method. For comparison, experimental values regarding the spatial resolution were determined by investigating the abrupt interface between Si(1 1 1) and AlN(0 0 0 1).