大型钢制立式储罐的导链式倒装法施工

介绍了导链式倒装法安装大型钢制立式储罐的原理及制作工艺流程。     

Alternating,all-trans polyenynes: Model compounds for poly(diacetylene)s with defined conjugation length

The syntheses of polyenynes as model compounds for poly(diacetylene)s (PDAs) are described. Variation of properties (UV–VIS, Raman, NMR and bond geometries) as a function of the chain length was investigated. After extrapolation to infinite chain length these data were compared to those for PDAs. From UV–VIS spectra a value of λ = 551 nm (2.25 eV) was calculated corresponding to the electronic transition of a single polyenyne chain. This energy is located at the low energy end of a yellow PDA solution spectrum. From Raman scattering v_(C?C) = 2108–2128 cm^?1 and v_(C?C) = 1505–1532 cm^?1 were calculated after extrapolation. Similarly sp-C¹³C NMR data yielded a shift of δ = 100 ppm. These data are almost identical to data known for yellow PDA solutions. Bond geometries are almost identical to those of poly(diacetylene)s and theoretical data.     

Skeleton chain coding for Chinese characters

The compression of Chinese characters is very important for Chinese office automation and desktop publishing. In this paper, various methods are used to compress 13,051 Chinese characters losslessly by coding their skeleton points. The skeleton points are composed of isolated points and curves. To trace every point in a curve once and consecutively is a NP problem. Therefore, we use contour path following and revisiting algorithms to trace skeleton curves with chain codes. The remaining isolated skeleton points are encoded by an Elias code. Our coding method has a better compression rate than that of conventional skeleton coding.     

刮板输送机接链用千斤拉的研究

针对刮板输送机的掐链、接链问题,研制出新型掐、接链用千斤拉,介绍了该装置的结构特点和工作原理,并对使用效果进行了分析。     

丙烯酸高碳醇酯的合成

介绍了降凝剂中间体丙烯酸高碳醇酯的合成和产品分离提纯方法。考察了合成条件对酯化反应的影响，结果表明，在原料丙烯酸与十八醇摩尔比1．2：1，阻聚剂对苯二酚用量占原料总量1．5％，催化剂对甲苯磺酸用量占原料总量1．5％，反应温度80-86℃，回流反应时间6h条件下，酯化率最高达89％。产品分离提纯方法与传统分离方法比较，所需分离时间短，洗涤用水量少，而产品收率远高于传统分离方法，达95％以上。     

Reducing Average and Peak Test Power Through Scan Chain Modification

Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.     

An introduction to Wu's method for mechanical theorem proving in geometry

Wu's algebraic method for mechanically proving geometry theorems is presented at a level as elementary as possible with sufficient examples for further understanding the complete method.The work reported here was supported by NSF Grant DCR-8503498.     

Jitter in ATM networks and its impact on peak rate enforcement

Cells arriving to an ATM network experience random delays due to queueing in upstream multiplexing stages, notably in customer premises. This is the phenomenon of jitter and the aim of the present paper is to study its influence on peak rate enforcement. We first introduce some general characterizations of jitter and then, describe two models of jittered flows based on simple queueing systems. We discuss the objectives of peak rate enforcement and study the impact of jitter on the dimensioning of jumping window and leaky bucket mechanisms. A useful synthetic characterization of jitter appears to be a remote quantile of the cell delay distribution expressed in units of the initial inter-cell interval.     

一种高速浮点加法器的设计实现

浮点加法器是协处理器的核心运算部件，是实现浮点指令各种运算的基础，其设计优化是提高浮点运算速度和精度的关键途径。文章从浮点加法器算法和电路实现的角度给出设计方法，并且提出动态与静态结合设计进位链的方案以及前导O预测面积与速度的折衷方法。动态与静态结合设计进位链的方法有效地降低了功耗，提高了速度，改善了性能。目前已经嵌入协处理器的设计中，并且流片测试成功。     

Approximating the problem, not the solution: An alternative view of point set matching

This work discusses the issue of approximation in point set matching. In general, one may have two classes of approximations when tackling a matching problem: (1) an algorithmic approximation which consists in using suboptimal procedures to infer the assignment, and (2), a representational approximation which involves a simplified and suboptimal model for the original data. Matching techniques have typically relied on the first approach by retaining the complete model and using suboptimal techniques to solve it. In this paper, we show how a technique based on using exact inference in simple Graphical Models, an instance of the second class, can significantly outperform instances of techniques from the first class. We experimentally compare this method with well-known Spectral and Relaxation methods, which are exemplars of the first class. We have performed experiments with synthetic and real-world data sets which reveal significant performance improvement in a wide operating range.