Development, implementation, and testing of fault detection strategies on the National Wind Technology Center’s controls advanced research turbines

The National Renewable Energy Laboratory’s National Wind Technology Center dedicates two 600 kW turbines for advanced control systems research. A fault detection system for both turbines has been developed, analyzed, and improved across years of experiments to protect the turbines as each new controller is tested. Analysis of field data and ongoing fault detection strategy improvements have resulted in a system of sensors, fault definitions, and detection strategies that have thus far been effective at protecting the turbines. In this paper, we document this fault detection system and provide field data illustrating its operation while detecting a range of failures. In some cases, we discuss the refinement process over time as fault detection strategies were improved. The purpose of this article is to share field experience obtained during the development and field testing of the existing fault detection system, and to offer a possible baseline for comparison with more advanced turbine fault detection controllers.     

Throughput and delay analysis of multi-channel wireless infrastructure networks

Wireless infrastructure networks (WINs) provide ubiquitous connectivity to mobile nodes in metro areas. The nodes in such backbone networks are often equipped with multiple transceivers to allow for concurrent transmissions in multiple orthogonal channels. In this study, we develop an analytical model for the estimation of the delay and throughput performance of wireless infrastructure networks employing slotted ALOHA channel access and slotted Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA) over multiple channels. The analytical model, which takes into account the correlation due to multi-hop transmissions, approximates the performance observed through simulations accurately.     

Image reconstruction using interval simulated annealing in electrical impedance tomography

Electrical impedance tomography (EIT) is an imaging technique that attempts to reconstruct the impedance distribution inside an object from the impedance between electrodes placed on the object surface. The EIT reconstruction problem can be approached as a nonlinear nonconvex optimization problem in which one tries to maximize the matching between a simulated impedance problem and the observed data. This nonlinear optimization problem is often ill-posed, and not very suited to methods that evaluate derivatives of the objective function. It may be approached by simulated annealing (SA), but at a large computational cost due to the expensive evaluation process of the objective function, which involves a full simulation of the impedance problem at each iteration. A variation of SA is proposed in which the objective function is evaluated only partially, while ensuring boundaries on the behavior of the modified algorithm.     

Design of high-speed two-stage cascode-compensated operational amplifiers based on settling time and open-loop parameters

Settling behavior of operational amplifiers is of great importance in many applications. In this paper, an efficient methodology for the design of high-speed two-stage operational amplifiers based on settling time is proposed. Concerning the application of the operational amplifier, it specifies proper open-loop circuit parameters to obtain the desired settling time and closed-loop stability. As the effect of transfer function zeros has been taken into account, the proposed methodology becomes more accurate in achieving the desired specifications. Simulation results are presented to show the effectiveness of the methodology.     

Gate sizing using geometric programming

A two-step transistor sizing optimization method based on geometric programming for delay/area minimization is presented. In the first step, Elmore delay is minimized using only minimum and maximum transistor size constraints. In the second step, the minimized delay found in the previous step is used as a constraint for area minimization. In this way, our method can target simultaneously both delay and area reduction. Moreover, by relaxing the minimized delay, one may further reduce area with small delay penalty. Gate sizing may be accomplished through transistor sizing tying each transistor inside a cell to a same scale factor. This reduces the solution space, but also improves runtime as less variables are necessary. To analyze this tradeoff between execution time and solution quality a comparison between gate sizing and transistor sizing is presented. In order to qualify our approach, the ISCAS??85 benchmark circuits are mapped to a 45?nm technology using a typical standard cell library. Gate sizing and transistor sizing are performed considering delay minimization. Gate sizing is able to reduce delay in 21?%, on average, for the same area and power values of the sizing provided by standard-cells library. Then, the transistor sizing is executed and delay can be reduced in 40.4?% and power consumption in 2.9?%, on average, compared to gate sizing. However, the transistor sizing takes about 23 times longer to be computed, on average, using a number of variables twice higher than gate sizing. Gate sizing optimizing area is executed considering a delay constraint. Three delay constraints are considered, the minimum delay given by delay optimization and delay 1 and 5?% higher than minimum delay. An energy/delay gain (EDG) metric is used to quantify the most efficient tradeoff. Considering the minimum delay, area (power) is reduced in 28.2?%, on average. Relaxing delay by just 1?%, area (power) is reduced in 41.7?% and the EDG metric is 41.7. Area can be reduced in 51?%, on average, relaxing delay by 5?% and EDG metric is 10.2.     

Sharp-rejection microstrip bandpass filters with multiple transmission zeros

A simple design of a sharp-rejection microstrip bandpass (BPF) filter is presented. By creating multiple transmission zeros in the lower and upper stopbands, sharp rejection characteristics are obtained. The basic filter unit consists of a single parallel coupled-line section and an open-ended stub. A lossless transmission line model approach is used to derive the design equations for frequency responses and transmission zero positions. The bandwidths are controllable by the zero locations that in turn are controlled by varying the impedances of the configuration. To validate theoretical predictions, two prototype BPFs operating at lower band 2.4 GHz of WLAN are fabricated in microstrip form.     

QoS provisioning for large-scale multi-ap WLANs

Large-scale deployment of IEEE 802.11 wireless LANs (WLANs) with a high density of access points (APs) has become commonplace due mainly to its potential for numerous benefits, such as ubiquitous service coverage, seamless handover, and improved link quality. However, the increased AP density can induce significant channel contention among neighboring cells, thus causing severe performance degradation and throughput imbalance between cells. There have been a plethora of research efforts to improve the WLAN performance, but most of them focused only on single WLAN environments without accounting for inter-cell contention. The de facto QoS-provisioning mechanism for WLANs, i.e., the Enhanced Distributed Channel Access (EDCA), is no exception to this. The EDCA focuses only on inter-flow priority distinction and has not considered the effect of inter-cell contention which significantly restricts its efficiency. This paper presents an enhanced QoS provisioning framework that takes into account inter-cell level differentiation as well as inter-flow level priority, which may be viewed as extension of QoS provisioning from a single-WLAN domain to a multi-WLAN domain. We also propose an architecture for managing multi-AP systems in which a central controller regulates the wireless channel occupancy of APs by adaptively configuring the cell-level QoS parameters. Our extensive simulation results show that the proposed inter-AP cooperative QoS scheme overcomes the limit of legacy 802.11e and provides a high level of fairness in large-scale densely-deployed WLANs.     

Design of 3.1–10.6 GHz ultra-wideband CMOS low noise amplifier with current reuse technique

A new low complexity ultra-wideband 3.1–10.6 GHz low noise amplifier (LNA), designed in a chartered 0.18 μm RFCMOS technology, is presented in this paper. The ultra-wideband LNA only consists of two simple amplifiers with an inter-stage inductor connected. The first stage utilizing a resistive current reuse and dual inductive degeneration techniques is used to attain a wideband input matching and low noise figure. A common source amplifier with inductive peaking technique as the second stage achieves high flat gain and wide the −3 dB bandwidth of the overall amplifier simultaneously. The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB, a high reverse isolation of −45 dB and a good input/output return losses are better than −10 dB in the frequency range of 3.1–10.6 GHz. An excellent noise figure (NF) of 2.8–4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V. An input-referred third-order intercept point (IIP3) is −7.1 dBm at 6 GHz. The chip area including testing pads is only 0.8 mm × 0.9 mm.     

Modern development methods and tools for embedded reconfigurable systems: A survey

Heterogeneous reconfigurable systems provide drastically higher performance and lower power consumption than traditional CPU-centric systems. Moreover, they do it at much lower costs and shorter times to market than non-reconfigurable hardware solutions. They also provide the flexibility that is often required for the engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, reconfigurable systems are adequate for a very broad class of applications across different industry sectors. What prevents the reconfigurable system paradigm from a broad proliferation is the lack of adequate development methodologies and electronics design tools for this kind of systems. The ideal would be a seamless compilation of a high-level computation process specification into an optimized mixture of machine code executed on traditional CPU-centric processors and on the application-specific decentralized parallel data-flow-dominated reconfigurable processors and hardware accelerators. Although much research and development in this direction was recently performed, the adequate methodologies and tools necessary to implement this compilation process as an effective and efficient hardware/software co-synthesis flow are unfortunately not yet in place. This paper focuses on the recent developments and development trends in the design methods and synthesis tools for reconfigurable systems. Reconfigurable system synthesis performs two basic tasks: system structure construction and application process mapping on the structure. It is thus more complex than standard (multi-)processor-based system synthesis for software-programmable systems that only involves application mapping. The system structure construction may involve the macro-architecture synthesis, the micro-architecture synthesis, and the actual hardware synthesis. Also, the application process mapping can be more complicated and dynamic in reconfigurable systems. This paper reviews the recent methods and tools for the macro- and micro-architecture synthesis, and for the application mapping of reconfigurable systems. It puts much attention to the relevant and currently hot topic of (re-)configurable application-specific instruction set processors (ASIP) synthesis, and specifically, ASIP instruction set extension. It also discusses the methods and tools for reconfigurable systems involving CPU-centric processors collaborating with reconfigurable hardware sub-systems, for which the main problem is to decide which computation processes should be implemented in software and which in hardware, but the hardware/software partitioning has to account for the hardware sharing by different computation processes and for the reconfiguration processes. The reconfigurable system area is a very promising, but quite a new field, with many open research and development topics. The paper reviews some of the future trends in the reconfigurable system development methods and tools. Finally, the discussion of the paper is summarized and concluded.     

Statistical analysis of large on-chip power grid networks by variational reduction scheme

One of the most critical challenges in today's CMOS VLSI design is the lack of predictability in chip performance at design stage. One of the process variabilities comes from the voltage drop variations in on-chip power distribution networks. In this paper, we present a novel analysis approach for computing voltage drops of large power grid networks under process variations. The new algorithm is very efficient and scalable for huge networks with a large number of variational variables. This approach, called variational extended truncated balanced realization (varETBR), is based on model order reduction techniques to reduce the circuit matrices before the variational simulation. It performs the parameterized reduction on the original system using variation-bearing subspaces. After the reduction, Monte Carlo based statistical simulation is performed on the reduced system and the statistical responses of the original system are obtained thereafter. varETBR calculates variational response Grammians by Monte Carlo based numerical integration considering both system and input source variations in generating the projection subspace. varETBR is very scalable for the number of variables and flexible for different variational distributions and ranges as demonstrated in experimental results. Experimental results, on a number of IBM benchmark circuits up to 1.6 million nodes, show that the varETBR can be 1900X faster than the Monte Carlo method and is much more scalable than one of the recently proposed approaches.