Establishing the relevancy of the bookkeeping libraries to thefunctional testing of computer implementations

We address issues related to the definition of faults, errors and failures and their separability, and attribution to the different development processes of computing systems. In particular, we deal with historical databases, which presumably contain certain data (i.e., test failure data) and describe the methodology that can be used to analyze the database and obtain the pertinent information. The validation method may be of particular importance, especially when information from the database needs to be extrapolated for a purpose other than the one for which the database was developed. Our methodology was used to evaluate the historical data collected during the development of the IBM 4381 and 9370 family of computers, and to extrapolate the faults found during the function testing     

Answering similarity queries in peer-to-peer networks

A variety of peer-to-peer (P2P) systems for sharing digital information are currently available and most of them perform searching by exact key matching. In this paper we focus on similarity searching and describe FuzzyPeer, a generic broadcast-based P2P system which supports a wide range of fuzzy queries. As a case study we present an image retrieval application implemented on top of FuzzyPeer. Users provide sample images whose sets of features are propagated through the peers. The answer consists of the top-k most similar images within the query horizon. In our system the participation of peers is ad hoc and dynamic, their functionality is symmetric and there is no centralized index.     

Simulating pavement structural condition using artificial neural networks

This article aims to investigate the feasibility of incorporating of an artificial neural network (ANN) as an innovative technique for modelling the pavement structural condition, into pavement management systems. For the development of the ANN, strain assessment criteria are set in order to characterise the structural condition of flexible asphalt pavements with regards to fatigue failure. This initial task is directly followed with the development of an ANN model for the prediction of strains primarily based on in situ field gathered data and not through the usage of synthetic databases. For this purpose, falling weight deflectometer (FWD) measurements were systematically conducted on a highway network, with ground-penetrating radar providing the required pavement thickness data. The FWD data (i.e. deflections) were back-analysed in order to assess strains that would be utilised as output data in the process of developing the ANN model. A paper exercise demonstrates how the developed ANN model combined with the suggested conceptual approach for characterising pavement structural condition with regard to strain assessment could make provisions for pavement management activities, categorising network pavement sections according to the need for maintenance or rehabilitation. Preliminary results indicate that the ANN technique could help assist policy decision makers in deriving optimum strategies for the planning of pavement infrastructure maintenance.     

Avoiding Conversion and Rearrangement Overhead in SIMD Architectures

Single-Instruction Multiple-Data (SIMD) instructions provide an inexpensive way to exploit the Data-Level Parallelism in multimedia applications. However, the performance improvement obtained by employing SIMD instructions is often limited because frequently many overhead instructions are required to bring data in a form amenable to SIMD processing. In this paper, we employ two techniques to overcome this limitation. The first technique, extended subwords, uses four extra bits for every byte in a media register. This allows many SIMD operations to be performed without overflow and avoids packing/unpacking conversion overhead. The second technique, Matrix Register File (MRF), allows flexible row-wise as well as column-wise access to the register file. It is useful for many two-dimensional multimedia algorithms such as the (I) Discrete Cosine Transform, 2 × 2 Haar Transform, and pixel padding. In addition, we propose a few new media instructions. Experimental results obtained by extending the SimpleScalar toolset show that these techniques improve performance by up to a factor of 4.5 compared to a conventional SIMD instruction set extension.     

Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration

In this paper, we study the performance impact of dynamic hardware reconfigurations for current reconfigurable technology. As a testbed, we target the Xilinx Virtex II Pro, the Molen experimental platform and the MPEG2 encoder as the application. Our experiments show that slowdowns of up to a factor 1000 are observed when the configuration latency is not hidden by the compiler. In order to avoid the performance decrease, we propose an interprocedural optimization that minimizes the number of executed hardware configuration instructions taking into account constraints such as the “FPGA-area placement conflicts” between the available hardware configurations. The presented algorithm allows the anticipation of hardware configuration instructions up to the application’s main procedure. The presented results show that our optimization produces a reduction of 3 to 5 order of magnitude of the number of executed hardware configuration instructions. Moreover, the optimization allows to exploit up to 97% of the maximal theoretical speedup achieved by the reconfigurable hardware execution.     

From application service provision to service-oriented computing: A study of the IT outsourcing evolution

IT outsourcing is not a new concept. Originating from the early 60’s in the form of time sharing, IT outsourcing has evolved to the application service provision (ASP) model, in the late 90’s to pure services in the beginning of the century. Services, and their major representative web services, are actually the next phase of the movement toward Internet-based componentized software, known in the not so distant past as ASP. As the continuous expansion of the Internet and its relating technologies creates new marketing opportunities, traditional monolithic architectures are giving way to service-oriented computing (SOC), the architecture that enables service provision. SOC permits the utilization of large systems which are comprised of self-containing building blocks: services. Services may be made public, searched, reused and combined to form complex business processes while in the same time retaining a significant level of flexibility. Services and SOC have emerged as a response to a fundamental shift in enterprise business culture that started at the late 90’s. Although they are promising as an IT outsourcing enabler, many issues need to be dealt with before they can be considered suitable for wide adoption. These issues are of technological, business, economic and cultural nature and they were also faced by ASPs in the past. It is worth revisiting the successes and failures of the ASP model in order to get a better understanding of the evolving IT outsourcing industry. In this work, we describe the evolution of service provision from its initial form as software application, through the application service provision era and towards the new trend of web services.     

Multimedia rectangularly addressable memory

We propose a scalable data alignment scheme incorporating module assignment functions and a generic addressing function for parallel access of randomly aligned rectangular blocks of data. The addressing function implicitly embeds the module assignment functions and it is separable, which potentially enables short critical paths and saves hardware resources. We also discuss the interface between the proposed memory organization and a linearly addressable memory. An implementation, suitable for MPEG-4 is presented and mapped onto an FPGA technology as a case study. Synthesis results indicate reasonably small hardware costs in the order of up to a few thousand FPGA slices for an exemplary 512/spl times/1024 two-dimensional (2-D) addressable space and a range of access pattern dimensions. Experiments suggest that speedups close to 8/spl times/ can be expected when compared to linear addressing schemes.