Determination and analysis of antigenic epitopes of prostate specific antigen (PSA) and human glandular kallikrein 2 (hK2) using synthetic peptides and computer modeling

In comparison with pyeloplasty, endourologic procedures for the treatment of ureteropelvic junction obstruction offer good success rates with less morbidity and a shorter hospitalization; however, studies have found lower success rates and increased complications in patients with crossing vessels. Conventional diagnostic angiography and intravenous urography have both been used to identify crossing vessels at the UPJ; but, a reliable, less invasive, less costly, and simpler preoperative procedure to identify crossing vessels is needed. Helical CT with CT angiography is a promising noninvasive technique for the identification of crossing vessels at the ureteropelvic junction, which can be used for surgical planning of endourologic treatment of UPJ obstruction.     

Parasympathetic neuropathy associated with left ventricular diastolic dysfunction in patients with insulin-dependent diabetes mellitus

BACKGROUND: As extracorporeal shock wave lithotripsy (ESWL) is frequently carried out on an outpatient basis, it is crucial to choose an adequate analgesic with less adverse effect. This study evaluated the use of three different intravenous agents: fentanyl, tramadol HCl and tenoxicam in ESWL. METHODS: One hundred and twenty patients undergoing lithotripsy were randomly assigned to receive either intravenous fentanyl 1 microgram/kg, tramadol HCl 1.5 mg/kg or tenoxicam 0.3 mg/kg before lithotripsy. Pain intensity was recorded using verbal rating pain scales (VRPS). Cases without adequate analgesia (VRPS > 4) or could not tolerate the pain, additional bolus of fentanyl 25 micrograms were given until adequate analgesia was achieved. Side effects were recorded as well. RESULTS: No significant differences were found among groups in demographic data, VRPS, number of total shock waves, cases with supplementary fentanyl, mean dose of supplementary fentanyl or the incidence of dizziness. However, the incidence of nausea or vomiting was significantly higher in fentanyl and tramadol groups comparing with tenoxicam group (15.0% and 25.0% vs. 0.0%). Oxygen saturation in fentanyl group was also significantly lower than the other two groups (p < 0.01). In addition, VRPS had a significant correlation with voltage intensities (p < 0.05). CONCLUSIONS: Lithotripsy can be satisfactorily performed by employing fentanyl, tramadol or tenoxicam for analgesia; tenoxicam apparently offers a better analgesic quality with less side effect. Furthermore, the need for stronger analgesia during larger voltage intensity should be tailored to the needs of the individuals.     

The Future of Simulation: A Field of Dreams

Due to the enormous complexity of computer systems, researchers use simulators to model system behavior and generate quantitative estimates of expected performance. Researchers also use simulators to model and assess the efficacy of future enhancements and novel systems. Arguably the most important tools available to computer architecture researchers, simulators offer a balance of cost, timeliness, and flexibility. Improving the infrastructure, benchmarking, and methodology of simulation - the dominant computer performance evaluation method - results in higher efficiency and let architects gain more insight into processor behavior. For these reasons, architecture researchers have increasingly relied on simulators     

基于超几何分解的随机运算系统分析方法

基于Bernoulli分布的方差及期望传递方程一直是随机运算系统的数学基础,针对这种传统分析方法在实际应用中的不准确性和片面性,该文提出一种全新的数学方法：超几何分解(hypergeometic decomposition),用来解决在更复杂情况下期望与方差在随机运算系统中的传播规律。基于超几何分解,提出4组更加精确的期望及方差传递方程,在数学上证明了随机运算体系更加广泛的适用性,并且通过随机运算系统在图像处理中的应用,提出了基于方差的系统评价方法,相比于传统按位仿真方法,基于方差的系统分析方法具有耗时短、准确和全面的优点。新的方差传递方程首次将随机信号源的类型引入性能分析,证明了具有特定码流长度的随机序列可以使系统性能达到最优。     

Comparing Processor Allocation Strategies in Multiprogrammed Shared-Memory Multiprocessors

Small-scale shared-memory multiprocessors are commonly used in a workgroup environment where multiple applications, both parallel and sequential, are executed concurrently while sharing the processors and other system resources. To utilize the processors efficiently, an effective allocation strategy is required. In this paper, we use performance data obtained from an SGI multiprocessor to evaluate several processor allocation strategies when running two parallel programs simultaneously. We examine gang scheduling (coscheduling), static space-sharing (space partitioning), and a dynamic allocation scheme called loop-level process control (LLPC) with three different dynamic allocation heuristics. We use regression analysis to quantify the measured data and thereby explore the relationship between the degree of parallelism of the application, specific system parameters (such as the size of the system), the processor allocation strategy, and the resulting performance. This study shows that dynamically partitioning the system using LLPC or similar heuristics provides better performance for applications with a high degree of parallelism than either gang scheduling or static space-sharing.     

Partitioning tasks between a pair of interconnected heterogeneous processors: A case study

With the variety of computer architectures available today, it is often difficult to determine which particular type of architecture will provide the best performance on a given application program. In fact, one type of architecture may be well suited to executing one section of a program while another architecture may be better suited to executing another section of the same program. One potentially promising approach for exploiting the best features of different computer architectures is to partition an application program to simultaneously execute on two or more types of machines interconnected with a high-speed communication network. A fundamental difficulty with this heterogeneous computing, however, is the problem of determining how to partition the application program across the interconnected machines. The goal of this paper is to show how a programmer or a compiler can use a model of a heterogeneous system to determine the machine on which each subtask should be executed. This technique is illustrated with a simple model that relates the relative performance of two heterogeneous machines to the communication time required to transfer partial results across their interconnection network. Experiments with a Connection Machine CM-200 demonstrate how to apply this model to partition two different application programs across the sequential front-end processor and the parallel back-end array.     

Exploiting the parallelism available in loops

Because a loop's body often executes many times, loops provide a rich opportunity for exploiting parallelism. This article explains scheduling techniques and compares results on different architectures. Since parallel architectures differ in synchronization overhead, instruction scheduling constraints, memory latencies, and implementation details, determining the best approach for exploiting parallelism can be difficult. To indicate their performance potential, this article surveys several architectures and compilation techniques using a common notation and consistent terminology. First we develop the critical dependence ratio to determine a loop's maximum possible parallelism, given infinite hardware. Then we look at specific architectures and techniques. Loops can provide a large portion of the parallelism available in an application program, since the iterations of a loop may be executed many times. To exploit this parallelism, however, one must look beyond a single basic block or a single iteration for independent operations. The choice of technique depends on the underlying architecture of the parallel machine and the characteristics of each individual loop     

Performance-based path determination for interprocessorcommunication in distributed computing systems

The different types of messages used by a parallel application program executing in a distributed computing system can each have unique characteristics so that no single communication network can produce the lowest latency for all messages. For instance, short control messages may be sent with the lowest overhead on one type of network, such as Ethernet, while bulk data transfers may be better suited to a different type of network, such as Fibre Channel or HIPPI. This work investigates how to exploit multiple heterogeneous communication networks that interconnect the same set of processing nodes using a set of techniques we call performance-based path determination (PBPD). The performance-based path selection (PBPS) technique selects the best (lowest latency) network among several for each individual message to reduce the communication overhead of parallel programs. The performance-based path aggregation (PBPA) technique, on the other hand, aggregates multiple networks into a single virtual network to increase the available bandwidth. We test the PBPD techniques on a cluster of SGI multiprocessors interconnected with Ethernet, Fibre Channel, and HiPPI networks using a custom communication library built on top of the TCP/IP protocol layers. We find that PBPS can reduce communication overhead in applications compared to using either network alone, while aggregating networks into a single virtual network can reduce communication latency for bandwidth-limited applications. The performance of the PBPD techniques depends on the mix of message sizes in the application program and the relative overheads of the networks, as demonstrated in our analytical models     

The impact of incorrectly speculated memory operations in a multithreaded architecture

The speculated execution of threads in a multithreaded architecture, plus the branch prediction used in each thread execution unit, allows many instructions to be executed speculatively, that is, before it is known whether they actually needed by the program. In this study, we examine how the load instructions executed on what turn out to be incorrectly executed program paths impact the memory system performance. We find that incorrect speculation (wrong execution) on the instruction and thread-level provides an indirect prefetching effect for the later correct execution paths and threads. By continuing to execute the mispredicted load instructions even after the instruction or thread-level control speculation is known to be incorrect, the cache misses observed on the correctly executed paths can be reduced by 16 to 73 percent, with an average reduction of 45 percent. However, we also find that these extra loads can increase the amount of memory traffic and can pollute the cache. We introduce the small, fully associative wrong execution cache (WEC) to eliminate the potential pollution that can be caused by the execution of the mispredicted load instructions. Our simulation results show that the WEC can improve the performance of a concurrent multithreaded architecture up to 18.5 percent on the benchmark programs tested, with an average improvement of 9.7 percent, due to the reductions in the number of cache misses.